Semiconductor device

• US 9,911,856 B2
• Filed: 10/07/2010
• Issued: 03/06/2018
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyanaga, Akiharu, Takahashi, Masahiro, Kishida, Hideyuki, Sakata, Junichiro
• Primary Examiner(s): Ahmadi, Mohsen
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US12/900,145
• Publication Number:
  US 20110084273A1
• Time in Patent Office: 2,707 Days
• Field of Search: 257 43-100, 438795, 438104
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

Claims

1. A semiconductor device comprising:

a transistor, the transistor comprising;

a gate electrode layer;

a gate insulating layer with a thickness equal to or larger than 100 nm and equal to or smaller than 350 nm;

an oxide semiconductor layer comprising indium, gallium, and zinc over the gate insulating layer;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer;

a silicon oxide layer over the source electrode layer and the drain electrode layer, the silicon oxide layer being in contact with the oxide semiconductor layer;

a mixed region between the oxide semiconductor layer and the silicon oxide; and

a protective insulating layer comprising nitrogen over and in contact with the silicon oxide layer,

wherein the mixed region comprises oxygen, silicon, and at least one of indium, gallium, and zinc,

wherein a thickness of the mixed region is from 1 nm to 10 nm, and

wherein a difference of a threshold voltage value of the transistor is 1 V or less, between before and after performance of a measurement in which a voltage of 30 V or −

30 V is applied to the gate electrode layer at a temperature of 85°

C. for 12 hours.

2. The semiconductor device according to claim 1, wherein the source electrode layer comprises an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W.

3. The semiconductor device according to claim 1, wherein a thickness of the mixed region is from 2 nm to 5 nm.

4. The semiconductor device according to claim 1, wherein the mixed region comprises a metal element M existing in a state any of M-OH, M-H, M-O—

Si—

H, and M-O—

Si—

OH.

5. A semiconductor device comprising:

a transistor, the transistor comprising;

a gate electrode layer;

a gate insulating layer with a thickness equal to or larger than 100 nm and equal to or smaller than 350 nm;

an oxide semiconductor layer comprising indium, gallium, and zinc over the gate insulating layer;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; and

a silicon oxide layer over and in contact with the oxide semiconductor layer,

wherein a mixed region is placed at an interface between the oxide semiconductor layer and the silicon oxide,

wherein a hydrogen concentration in the interface is 5×

10¹⁹/cm³ or lower,

wherein the mixed region comprises oxygen, silicon, and at least one of indium, gallium, and zinc,

wherein a thickness of the mixed region is from 1 nm to 10 nm, and

wherein a difference of a threshold voltage value of the transistor is 1 V or less, between before and after performance of a measurement in which a voltage of 30 V or −

30 V is applied to the gate electrode layer at a temperature of 85°

C. for 12 hours.

6. The semiconductor device according to claim 5, wherein the source electrode layer comprises an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W.

7. The semiconductor device according to claim 5, wherein a thickness of the mixed region is from 2 nm to 5 nm.

8. The semiconductor device according to claim 5, wherein the mixed region comprises a metal element M existing in a state any of M-OH, M-H, M-O—

Si—

H, and M-O—

Si—

OH.