Semiconductor device and method for manufacturing the semiconductor device

• US 9,911,865 B2
• Filed: 11/20/2015
• Issued: 03/06/2018
• Est. Priority Date: 09/01/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/947,109
• Publication Number:
  US 20160079439A1
• Time in Patent Office: 837 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium and zinc;

a source region over the oxide semiconductor layer;

a drain region over the oxide semiconductor layer, wherein each of the source region and the drain region comprises indium and zinc;

a source electrode layer on the source region; and

a drain electrode layer on the drain region,

wherein each of the source region and the drain region comprises crystal grains having a diameter of 1 nm to 10 nm,

wherein the oxide semiconductor layer extends beyond outer side edges of the source electrode layer and the drain electrode layer.

2. The semiconductor device according to claim 1, wherein an oxygen concentration in the oxide semiconductor layer at an interface with the gate insulating layer is higher than at a portion distant from the interface.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer further comprises gallium.

4. The semiconductor device according to claim 1, wherein each of the source electrode layer and the drain electrode layer comprises a metal selected from the group consisting of aluminum, copper, titanium and molybdenum.

5. The semiconductor device according to claim 1, wherein an oxygen concentration in the source region and the drain region is lower than an oxygen concentration in the oxide semiconductor layer.

6. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium, gallium and zinc;

a source region over the oxide semiconductor layer;

a drain region over the oxide semiconductor layer, wherein each of the source region and the drain region comprises indium and zinc;

a source electrode layer on the source region; and

a drain electrode layer on the drain region, wherein each of the source electrode layer and the drain electrode layer comprises copper,

wherein the oxide semiconductor layer extends beyond outer side edges of the source electrode layer and the drain electrode layer.

7. The semiconductor device according to claim 6, wherein each of the source region and the drain region comprises crystal grains having a diameter of 1 nm to 10 nm.

8. The semiconductor device according to claim 6, wherein an oxygen concentration in the oxide semiconductor layer at an interface with the gate insulating layer is higher than at a portion distant from the interface.

9. The semiconductor device according to claim 6, wherein each of the source region and the drain region further comprises gallium.

10. The semiconductor device according to claim 6, wherein the gate electrode layer comprises a metal selected from the group consisting of titanium, molybdenum, chromium, tantalum, tungsten, aluminum and an alloy thereof.

11. The semiconductor device according to claim 6, wherein an oxygen concentration in the source region and the drain region is lower than an oxygen concentration in the oxide semiconductor layer.

12. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium, gallium and zinc;

a first oxide layer over the oxide semiconductor layer;

a second oxide layer over the oxide semiconductor layer, wherein each of the first oxide layer and the second oxide layer comprises indium and zinc;

a first conductive layer on the first oxide layer;

a second conductive layer on the second oxide layer; and

an insulating film over the first conductive layer and the second conductive layer, wherein the insulating film is in contact with an upper surface of the oxide semiconductor layer between the first conductive layer and the second conductive layer,

wherein each of the first conductive layer and the second conductive layer comprises copper, and

wherein the oxide semiconductor layer extends beyond outer side edges of the first conductive layer and the second conductive layer.

13. The semiconductor device according to claim 12, wherein each of the first oxide layer and the second oxide layer comprises crystal grains having a diameter of 1 nm to 10 nm.

14. The semiconductor device according to claim 12, wherein an oxygen concentration in the oxide semiconductor layer at an interface with the gate insulating layer is higher than at a portion distant from the interface.

15. The semiconductor device according to claim 12, wherein each of the first oxide layer and the second oxide layer further comprises gallium.

16. The semiconductor device according to claim 12, wherein the gate electrode layer comprises a metal selected from the group consisting of titanium, molybdenum, chromium, tantalum, tungsten, aluminum and an alloy thereof.

17. The semiconductor device according to claim 12, wherein an oxygen concentration in the first oxide layer and the second oxide layer is lower than an oxygen concentration in the oxide semiconductor layer.