Hold up architecture for power supply with DC-DC converter

• US 9,912,239 B2
• Filed: 07/21/2016
• Issued: 03/06/2018
• Est. Priority Date: 07/21/2016
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Beedu, Nishanth, Prabhu K, Prashant Purushotham, Marotta, Joseph, Gramata, Peter, Young, Stephen
• Primary Examiner(s): PATEL, RAJNIKANT B
• Application Number:
  US15/215,986
• Publication Number:
  US 20180026536A1
• Time in Patent Office: 593 Days
• Field of Search: 363 16- 17, 363 2104, 363 2107, 363 2111, 363 65, 363 71- 76, 323222, 323212, 323241, 323237, 323271, 323282-285, 307 91, 307 71, 361 90, 361 937, 361 939
• CPC Class Codes: H02J 2207/20 Charging or discharging characterised by the power electronics converter
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: H02M 1/0096 Means for increasing hold-up time, i.e. the duration of time that a converter's output will remain within regulated limits following a loss of input power
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection

Abstract

A power supply includes a DC-DC converter, a boost converter, an energy storage element; and a voltage clamping circuit. The DC-DC converter is connected to a power source with an output voltage in a first voltage range. The voltage clamper circuit is configured to discharge at least a portion of energy of the energy storage element and to produce current at a clamped output voltage range that is substantially equal to the first voltage range. The discharged energy provides hold-up time for the power supply.

Claims

1. A voltage clamping circuit for a power supply comprising:

an input connection;

an output connection;

two semiconductor clamping switches connected in a series pass configuration and interposed between the input connection and the output connection; and

a first semiconductor under-voltage detection switch and a second semiconductor under-voltage detection switch, along with a resistor feedback circuit interposed between the input connection and the output connection.

2. The voltage clamping circuit of claim 1 wherein the clamping switches are Metal-Oxide Semiconductor Field-Effect transistors (MOSFETs).

3. The voltage clamping circuit of claim 1 further comprising:

the first semiconductor under-voltage detection switch connected in series with one of the clamping switches; and

two diodes connected with the first semiconductor under-voltage detection switch to reduce temperature dependence of forward voltage drop of the first semiconductor under-voltage detection switch.

4. The voltage clamping circuit of claim 3 wherein the two diodes are Schottky diodes.

5. The voltage clamping circuit of claim 3 wherein the first semiconductor under-voltage detection switch is a bipolar junction transistor (BJT).

6. The voltage clamping circuit of claim 3:

wherein the voltage clamping circuit includes an operational amplifier with a built-in reference; and

wherein the operational amplifier is interconnected with the first semiconductor under-voltage detection switch and the output connection to enable operation of the first semiconductor under-voltage detection switch responsively to a condition in which power is not provided at the output connection at a voltage within a desired voltage range.