Please download the dossier by clicking on the dossier button x
×

Three dimensional integrated circuits

  • US 9,912,336 B2
  • Filed: 11/23/2015
  • Issued: 03/06/2018
  • Est. Priority Date: 07/08/2002
  • Status: Active Grant
First Claim
Patent Images

1. A device comprising:

  • a programmable layer including a programmable circuit comprising a plurality of input programming nodes operable to program the programmable circuit in response to respective logic values; and

    a hard-wire layer including a wire pattern hard-wired to the plurality of input programming nodes to hard-wire the respective logic values and to configure the programmable circuit with a hard-wired predetermined logical and routing functionality.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×