Three dimensional integrated circuits

• US 9,912,336 B2
• Filed: 11/23/2015
• Issued: 03/06/2018
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US14/949,679
• Publication Number:
  US 20160134288A1
• Time in Patent Office: 834 Days
• Field of Search: None
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Claims

1. A device comprising:

a programmable layer including a programmable circuit comprising a plurality of input programming nodes operable to program the programmable circuit in response to respective logic values; and

a hard-wire layer including a wire pattern hard-wired to the plurality of input programming nodes to hard-wire the respective logic values and to configure the programmable circuit with a hard-wired predetermined logical and routing functionality.

2. The device of claim 1, wherein the programmable layer further comprises a second programmable circuit including a second plurality of input programming nodes, and wherein the wire pattern is hard-wired to the second plurality of input programming nodes to configure the second programmable circuit with a second hard-wired predetermined logical and routing functionality.

3. The device of claim 1, further comprising:

another programmable layer including a second programmable circuit comprising a second plurality of input programming nodes, wherein the wire pattern is hard-wired to the second plurality of input programming nodes to configure the second programmable circuit with a second hard-wired predetermined logical and routing functionality.

4. The device of claim 1, further comprising:

a substrate, wherein the programmable layer and the hard-wire layer are positioned in a vertically-stacked arrangement relative to the substrate.

5. The device of claim 1, wherein the wire pattern is further operable to connect a logic low signal to the programmable circuit.

6. The device of claim 5, wherein the wire pattern is further operable to connect a logic high signal to the programmable circuit.

7. The device of claim 1, wherein the wire pattern comprises a plurality of metal layers, and wherein programmable logic of the programmable layer is converted to hard-wired logic by the wire pattern.

8. A method comprising:

forming a programmable layer including a programmable circuit comprising a plurality of input programming nodes operable to program the programmable circuit in response to respective logic values;

forming a hard-wire layer including a wire pattern; and

hard-wiring the wire pattern to the plurality of input programming nodes to hard-wire the respective logic values and to configure the programmable circuit with a hard-wired predetermined logical and routing functionality.

9. The method of claim 8, wherein the programmable layer further comprises a second programmable circuit including a second plurality of input programming nodes, and further comprising:

hard-wiring the wire pattern to the second plurality of input programming nodes to configure the second programmable circuit with a second hard-wired predetermined logical and routing functionality.

10. The method of claim 8, further comprising:

forming another programmable layer including a second programmable circuit comprising a second plurality of input programming nodes; and

hard-wiring the wire pattern to the second plurality of input programming nodes to configure the second programmable circuit with a second hard-wired predetermined logical and routing functionality.

11. The method of claim 8, further comprising:

providing a substrate; and

positioning the programmable layer and the hard-wire layer in a vertically-stacked arrangement relative to the substrate.

12. The method of claim 8, wherein said hard-wiring comprises connecting the wire pattern to the programmable circuit to receive a logic low signal.

13. The method of claim 12, wherein said hard-wiring further comprises connecting the wire pattern to the programmable circuit to receive a logic high signal.

14. The method of claim 8, wherein the wire pattern comprises a plurality of metal layers, and wherein programmable logic of the programmable layer is converted to hard-wired logic by the wire pattern.

15. A method comprising:

forming a layer including programmable logic comprising a plurality of input programming nodes operable to program the programmable logic in response to respective logic values; and

converting the programmable logic to hard-wired logic, wherein said converting includes;

forming a hard-wire layer comprising a wire pattern; and

hard-wiring the wire pattern to the plurality of input programming nodes to hard-wire the respective logic values and to configure the programmable logic with a hard-wired predetermined logical and routing functionality to form the hard-wired logic.

16. The method of claim 15, further comprising:

forming another layer including second programmable logic comprising a second plurality of input programming nodes, wherein said hard-wiring further includes;

hard-wiring the wire pattern to the second plurality of input programming nodes to configure the second programmable logic with a second hard-wired predetermined logical and routing functionality to form the hard-wired logic.

17. The method of claim 15, further comprising:

providing a substrate; and

positioning the layer and the hard-wire layer in a vertically-stacked arrangement relative to the substrate.

18. The method of claim 15, wherein said hard-wiring the wire pattern comprises coupling the wire pattern to the programmable logic to receive a logic low signal.

19. The method of claim 18, wherein said hard-wiring the wire pattern further comprises coupling the wire pattern to the programmable logic to receive a logic high signal.

20. The method of claim 15, wherein the wire pattern comprises a plurality of metal layers.