Printing complex electronic circuits using a patterned hydrophobic layer

• US 9,913,371 B2
• Filed: 01/13/2017
• Issued: 03/06/2018
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: NthDegree Technologies Worldwide Inc.
• Original Assignee: NthDegree Technologies Worldwide Inc.
• Inventors: Ray, William Johnstone, Blanchard, Richard Austin, Lowenthal, Mark David, Oraw, Bradley Steven
• Primary Examiner(s): Tran, Binh
• Application Number:
  US15/405,601
• Publication Number:
  US 20170135214A1
• Time in Patent Office: 417 Days
• Field of Search: 361748, 361760, 361761, 438107, 438110, 438111, 438112, 438127, 438128
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/25105 Connecting at different heights
• CPC Class Codes: H01L 2224/25174 Stacked arrangements
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82101 by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82104 using screen printing
• CPC Class Codes: H01L 2224/82143 Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95101 in a liquid medium
• CPC Class Codes: H01L 2224/95102 being a colloidal droplet
• CPC Class Codes: H01L 2224/95115 using a roll-to-roll transfer technique
• CPC Class Codes: H01L 2224/95143 Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/95146 by surface tension
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12 : Passive devices, e.g. 2 terminal devices
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13 : Discrete devices, e.g. 3 terminal devices
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 33/20 : with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H05K 1/0296 : Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18

Abstract

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Claims

1. A circuit comprising:

a substrate;

a first material overlying the substrate and patterned to define first openings;

a plurality of separate groups of pre-formed, semiconductor electrical devices that have been mixed in a first solution, deposited over the substrate, and cured,

each group containing a plurality of substantially identical electrical devices connected in parallel within each group, the electrical devices being randomly distributed within each group on the substrate,

wherein the first material prevents wetting by the first solution such that the first solution resides only within the first openings, resulting in each group of the substantially identical electrical devices being defined by the first openings in the first material;

an interconnection conductor pattern that is programmable to interconnect at least some of the groups together to achieve an electrical function;

one or more input terminals for supplying an input signal; and

one or more output terminals for supplying an output signal, wherein the input signal is transformed by the electrical devices after the interconnection conductor pattern is programmed, and the transformed signal is output at the one or more output terminals.

2. The circuit of claim 1 wherein the first material is hydrophobic.

3. The circuit of claim 1 wherein the first material is omniphobic.

4. The circuit of claim 1 further comprising a first conductor layer that is defined by the first openings in the first material, where in the first conductor layer electrically contacts the electrical devices.

5. The circuit of claim 1 further comprising:

a second material deposited over the first material and patterned to have second openings; and

a conductive material deposited in the second openings, the conductive material being deposited in a second solution,

wherein the second material prevents wetting by the second solution such that the second solution resides only within the second openings, resulting in the conductive material being defined by the second openings in the second material.

6. The circuit of claim 1 wherein each group has at least one electrical connector that extends from its associated group, wherein each electrical connector terminates at a termination area, and wherein the interconnection conductor pattern comprises conductors that electrically connect to the groups at the termination area.

7. The circuit of claim 1 wherein the devices are deposited by printing.

8. The circuit of claim 1 wherein the devices have a largest dimension less than 200 microns.

9. The circuit of claim 1 wherein each group in the plurality of separate groups contains substantially identical first devices, wherein the plurality of separate groups is a first plurality of separate groups, the circuit further comprising a second plurality of separate groups, wherein the groups with the second plurality contain second devices different from the first devices.

10. The circuit of claim 1 wherein the devices comprises at least one of transistors or diodes.

11. The circuit of claim 1 wherein the devices are 3-terminal devices having a first electrode, a second electrode, and a third electrode, wherein the first electrode is a bottom electrode of the devices, the third electrode is a top electrode of the devices, and the second electrode is an intermediate electrode located vertically between the top electrode and the bottom electrode, the circuit further comprising:

a first conductor layer over the substrate, wherein the first electrode of the devices is electrically connected to the first conductor layer;

a first dielectric layer overlying the first conductor layer;

a second conductor layer overlying the first dielectric layer to electrically contact the second electrode;

a second dielectric layer over the second conductor layer; and

a third conductor layer overlying the second dielectric layer to electrically contact the third electrode,

wherein the devices are electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer.

12. The circuit of claim 1 wherein the substrate has a patch area, wherein each group has at least one electrical connector that extends from its associated group and terminates in the patch area, and wherein the interconnection conductor pattern comprises conductors that electrically connect to the groups at the patch area.

13. The circuit of claim 1 wherein the interconnection conductor pattern interconnects the groups to form logic gates.

14. The circuit of claim 1 wherein the interconnection conductor pattern interconnects the groups to perform logic functions.

15. The circuit of claim 1 wherein the interconnection conductor pattern interconnects the groups to create analog circuits.

16. A method for forming a circuit comprising:

patterning a first material overlying a substrate to define first openings;

depositing a first solution over the first material, the first solution containing pre-formed, semiconductor electrical devices,

wherein the first material prevents wetting by the first solution such that the first solution resides only within the first openings;

curing the first solution containing pre-formed, semiconductor electrical devices such that electrical terminals of the electrical devices electrically contact a first conductor layer overlying the substrate,

the electrical devices located in each of the first openings forming groups of the electrical devices defined by the first openings in the first material, the electrical devices in each group being connected in parallel; and

forming at least one conductor layer to enable interconnecting at least some of the groups to achieve an electrical function.

17. The method of claim 16 further comprising:

forming one or more input terminals for supplying an input signal; and

forming one or more output terminals for supplying an output signal, wherein the input signal is transformed by the electrical devices after an interconnection conductor pattern is programmed, and the transformed signal is output at the one or more output terminals.

18. The method of claim 16 further comprising interconnecting the groups to form logic gates.

19. The method of claim 16 wherein the first material is omniphobic.

20. The method of claim 16 wherein the first material is hydrophobic.