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Bus arbitration with routing and failover mechanism

  • US 9,916,213 B1
  • Filed: 04/16/2015
  • Issued: 03/13/2018
  • Est. Priority Date: 03/15/2013
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a plurality of bus masters comprising a first bus master, a second bus master, a third bus master, and a fourth bus master wherein the bus masters control slave devices and a plurality of bus arbiters configured to support failover, wherein the plurality of bus arbiters comprises a first bus arbiter coupled to the first bus master and the second bus master and a second bus arbiter coupled to the third bus master and fourth bus master;

    wherein the first bus master is directly coupled by a first path to the first bus arbiter;

    wherein the second bus master is directly coupled by a second path to the first bus arbiter;

    wherein the third bus master is directly coupled by a third path to the second bus arbiter;

    wherein the fourth bus master is directly coupled by a fourth path to the second bus arbiter; and

    a central processing unit (CPU) coupled to the bus arbiters;

    wherein the CPU is coupled by a link to the first bus arbiter and to the second bus arbiter;

    wherein the CPU communicates with the first bus arbiter and the second bus arbiter;

    wherein the slave devices comprise a first group of slave devices and a second group of slave devices;

    wherein the first bus master and second bus master control the first group of slave devices; and

    wherein the third bus master and fourth bus master control the second group of slave devices;

    wherein the CPU is configured to execute the failover in response to a bus failure or in response to idle, inactive, or unused buses coupled to the second bus arbiter, wherein the failover comprises the second bus arbiter failing over to the first bus arbiter so that the first bus arbiter takes over a role of the second bus arbiter.

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