Ultra low power architecture to support always on path to memory

• US 9,916,876 B2
• Filed: 07/21/2014
• Issued: 03/13/2018
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Partiwala, Suketu R., Kalluraya, Prashanth, Fleming, Bruce L., Thakkar, Shreekant S., Shoemaker, Kenneth D., Lakshmanamurthy, Sridhar, Yehia, Sami, Ray, Joydeep
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/336,128
• Publication Number:
  US 20160019936A1
• Time in Patent Office: 1,331 Days
• Field of Search: 365227, 365226
• CPC Class Codes: G06F 1/189 Power distribution
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Claims

1. An apparatus with an ultra low power architecture, comprising:

a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail; and

a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the second power supply rail, wherein the second power supply rail is to be always on, always available, and low power when compared to the first power supply rail;

a coherent data path to a memory subsystem from the plurality of autonomous subsystems; and

a non-coherent data path to a memory subsystem from the plurality of autonomous subsystems.

2. The apparatus of claim 1, wherein the apparatus is a system on chip.

3. The apparatus of claim 1, wherein the autonomous subsystems directly access a memory of the apparatus.

4. The apparatus of claim 1, wherein a memory access by the plurality of autonomous subsystems does not exit an S0ix system state.

5. The apparatus of claim 1, wherein an autonomous subsystem is active during a deep S0ix sleep state.

6. The apparatus of claim 1, wherein the plurality of autonomous subsystems are placed on a same fabric of the apparatus.

7. The apparatus of claim 1, wherein the plurality of autonomous subsystems are moved to a separate companion die of the apparatus.

8. The apparatus of claim 1, wherein the plurality of autonomous subsystems include sensor hub, modem, audio, any subsystem that can access memory independently, or any combination thereof.

9. The apparatus of claim 1, wherein the apparatus is a mobile device.

10. The apparatus of claim 1, wherein a high bandwidth path to a memory is enabled by the first power supply rail.

11. The apparatus of claim 1, wherein a low bandwidth path to a memory is enabled using the always on, always available second power supply rail.

12. A power management integrated circuit (PMIC) of a system, operable to provide a plurality of power states, wherein the power management integrated circuit is to transition an autonomous subsystem from a sleep state to an active state, and wherein the autonomous subsystem is active and powered by a low power always on power supply that is low power when compared to other power of the system, while a second subsystem is to remain in the sleep state, wherein the low power always on power supply is to power a non-coherent data path to memory.

13. The power management integrated circuit of claim 12, wherein the autonomous subsystem uses a non-coherent data path to access memory during a low power use case.

14. The power management integrated circuit of claim 12, wherein the power management integrated circuit is to remove the second subsystem from the sleep state when the autonomous subsystem is to provide coherent data on a coherent data path to memory.

15. The power management integrated circuit of claim 12, wherein the power management integrated circuit does not toggle a main power rail in response to a non-coherent memory access by the autonomous subsystem.

16. The power management integrated circuit of claim 12, wherein the power management integrated circuit manages a plurality of autonomous subsystems.

17. A method for providing an ultra low power architecture, comprising:

enabling a first path to memory on a mobile system on chip, wherein the first path to memory is powered by a main power rail and the first path to memory is a high bandwidth, high latency data path; and

enabling a second path to memory on the mobile system on chip, wherein the path to memory is powered by a second low power, always on power rail, that is low power when compared to the main power rail.

18. The method of claim 17, wherein second path to memory is a low bandwidth, low latency data path.

19. The method of claim 17, wherein an autonomous subsystem accesses the memory using the second path to memory, without a second subsystem exiting an S0ix system state.

20. The method of claim 17, wherein the first path to memory is a coherent data path to the memory subsystem from a plurality of autonomous subsystems.

21. The method of claim 17, wherein the second path to memory is a non-coherent data path to a memory subsystem from a plurality of autonomous subsystems.

22. The method of claim 17, wherein the second path to memory is accessed by a plurality of autonomous subsystems that are placed on a same fabric of the mobile system on chip.