Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package

• US 9,917,073 B2
• Filed: 06/29/2016
• Issued: 03/13/2018
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Mohammed, Ilyas
• Primary Examiner(s): MUSE, ISMAIL A
• Application Number:
  US15/196,635
• Publication Number:
  US 20160307878A1
• Time in Patent Office: 622 Days
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387

Abstract

A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.

Claims

1. A method for making a microelectronic package, comprising:

forming a plurality of electrically conductive interconnects through first and second encapsulated microelectronic elements, each of the microelectronic elements including;

a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces;

an encapsulant contacting at least the edge surface of the respective semiconductor die and extending in at least one of the lateral directions from the edge surface, the front face and the back face of the respective semiconductor die being uncovered by the encapsulant; and

electrically conductive elements extending from the contacts of the semiconductor die in at least one of the lateral directions to locations overlying the encapsulant;

wherein the first and second microelectronic elements are affixed to one another by a bonding layer of dielectric material that extends between and contacts dielectric material at confronting surfaces of the first and second microelectronic elements such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies and at least some conductive elements of at least one of the microelectronic elements are abutting the bonding layer between the confronting surfaces, the encapsulants of the first and second microelectronic elements defining first and second opposite and outwardly facing surfaces, respectively, remote from the bonding layer, the first outwardly facing surface extending substantially co-planar with the front face or the back face of the semiconductor die of the first microelectronic element, and the second outwardly facing surface extending substantially co-planar with the front face or the back face of the semiconductor die of the second microelectronic element; and

wherein the conductive interconnects are formed through the encapsulants of the first and second microelectronic elements, each conductive interconnect extending through an opening having a continuous interior surface extending from the first outwardly facing surface through the encapsulant of the first microelectronic element, and through the bonding layer and the encapsulant of the second microelectronic element to the second outwardly facing surface, wherein at least one of the conductive interconnects is electrically coupled with at least one of the conductive elements at a location adjacent the bonding layer and thereby electrically connected with at least one semiconductor die of the first and second microelectronic elements.

2. The method of claim 1, wherein the conductive interconnects are formed by laser etching the openings through the encapsulants of the first and second microelectronic elements and through respective ones of the conductive elements and by at least partially filling the openings with a conductive metal.

3. The method of claim 1, further including affixing the first and second microelectronic elements to one another such that the front faces confront one another.

4. The method of claim 1, further including affixing the first and second microelectronic elements to one another such that the front face of the second microelectronic element confronts the back face of the first microelectronic element.

5. The method of claim 1, further including affixing the first and second microelectronic elements to one another such that the back faces confront one another.

6. The method of claim 1, wherein the conductive interconnects are formed to include first conductive interconnects connected by respective conductive elements to the first microelectronic element and second conductive interconnects connected by respective conductive elements to the second microelectronic element.

7. The method of claim 6, wherein a quantity of first conductive interconnects formed in the package is equal to a quantity of second conductive vias formed in the package.

9. The method of claim 1, further including forming the electrically conductive elements.

10. The method of claim 9, wherein forming the electrically conductive elements includes forming the conductive elements on at least one of the first or second microelectronic elements prior to a step of affixing the microelectronic elements together.

11. The method of claim 9, wherein forming the electrically conductive elements includes forming the conductive elements on a dielectric region overlying at least one of the first or second microelectronic elements before a step of affixing the microelectronic elements together.

8. A method for making a microelectronic package, comprising:

forming a plurality of electrically conductive interconnects through first and second encapsulated microelectronic elements, each of the microelectronic elements including;

a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces;

an encapsulant contacting at least the edge surface of the respective semiconductor die and extending in at least one of the lateral directions from the edge surface; and

electrically conductive elements extending from the contacts of the semiconductor die in at least one of the lateral directions to locations overlying the encapsulant;

wherein the first and second microelectronic elements are affixed to one another by a bonding layer of dielectric material that extends between and contacts dielectric material at confronting surfaces of the first and second microelectronic elements such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies and at least some conductive elements of at least one of the microelectronic elements are abutting the bonding layer between the confronting surfaces, the encapsulants of the first and second microelectronic elements defining first and second opposite and outwardly facing surfaces, respectively, remote from the bonding layer; and

wherein the conductive interconnects are formed through the encapsulants of the first and second microelectronic elements, each conductive interconnect extending through an opening having a continuous interior surface extending from the first outwardly facing surface through the encapsulant of the first microelectronic element, and through the bonding layer and the encapsulant of the second microelectronic element to the second outwardly facing surface, wherein at least one of the conductive interconnects is electrically coupled with at least one of the conductive elements at a location adjacent the bonding layer and thereby electrically connected with at least one semiconductor die of the first and second microelectronic elements,

wherein the conductive interconnects are formed to include first conductive interconnects connected by respective conductive elements to the first microelectronic element and second conductive interconnects connected by respective conductive elements to the second microelectronic element, and

wherein the conductive interconnects are further formed to include third conductive interconnects that are free from other electrical connections within the package.

12. A method for making a microelectronic assembly, comprising:

making a first microelectronic package by a method including;

forming a plurality of electrically conductive interconnects through first and second encapsulated microelectronic elements, each of the microelectronic elements including;

a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces;

an encapsulant contacting at least the edge surface of the respective semiconductor die and extending in at least one of the lateral directions from the edge surface, the front face and the back face of the respective semiconductor die being uncovered by the encapsulant; and

electrically conductive elements including metalized vias extending from the contacts of the semiconductor die in at least one of the lateral directions to locations overlying the encapsulant;

wherein the first and second microelectronic elements are affixed to one another by a bonding layer of dielectric material that extends between and contacts dielectric material at confronting surfaces of the first and second microelectronic elements such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies and at least some conductive elements of at least one of the microelectronic elements are abutting the bonding layer between the confronting surfaces, the encapsulants of the first and second microelectronic elements defining first and second opposite and outwardly facing surfaces, respectively, remote from the bonding layer, the first outwardly facing surface extending substantially co-planar with the front face or the back face of the semiconductor die of the first microelectronic element, and the second outwardly facing surface extending substantially co-planar with the front face or the back face of the semiconductor die of the second microelectronic element; and

wherein the conductive interconnects are formed through the encapsulants of the first and second microelectronic elements, each conductive interconnect extending through an opening having a continuous interior surface extending from the first outwardly facing surface through the encapsulant of the first microelectronic element, and through the bonding layer and the encapsulant of the second microelectronic element to the second outwardly facing surface, wherein at least one of the conductive interconnects is electrically coupled with at least one of the conductive elements at a location adjacent the bonding layer and thereby electrically connected with at least one semiconductor die of the first and second microelectronic elements;

positioning the first microelectronic package over a second microelectronic package including a logic chip electrically connected with terminals exposed on a first surface of the second package and package contacts exposed on a second surface of the second microelectronic package; and

joining ends of the conductive interconnects of the first microelectronic package that face the second microelectronic package with the terminals of the second microelectronic package using a plurality of conductive joining elements.

13. The method of claim 12, further including positioning a third microelectronic package over the first microelectronic package, the third microelectronic package including terminals exposed on a surface thereof that is positioned to confront the first package, the method further including joining terminals of the third microelectronic package with ends of the conductive interconnects that are disposed toward the third microelectronic package.

14. The method of claim 13, wherein the conductive interconnects are formed to include first conductive interconnects connected by respective conductive elements to the first microelectronic element, second conductive interconnects connected by respective conductive elements to the second microelectronic element, and third conductive interconnects that are free from other electrical connections within the first microelectronic package, the terminals of the third microelectronic package are joined with ends of the third conductive interconnects, the third conductive interconnects electrically connecting the third microelectronic package to the second microelectronic package.