Semiconductor device having staggered pillars

• US 9,917,094 B2
• Filed: 10/22/2015
• Issued: 03/13/2018
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Wookhyoung, Chun, Jongsik, Shim, Sunil, Ahn, Jaeyoung, Lee, Juyul, Hwang, Kihyun, Kim, Hansoo, Lee, Woonkyung, Jang, Jaehoon, Cho, Wonseok
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US14/920,223
• Publication Number:
  US 20160049419A1
• Time in Patent Office: 873 Days
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Claims

1. A semiconductor memory device comprising:

a plurality of horizontal electrodes including an upper selection gate and cell gates below the upper selection gate;

a plurality of insulating patterns alternatingly stacked with the plurality of horizontal electrodes; and

an array of pillars formed in the plurality of insulating patterns and the plurality of horizontal electrodes, the array of pillars comprising;

a first column of pillars disposed along a first direction when viewed from a top of the semiconductor memory device;

a second column of pillars disposed along the first direction and adjacent to the first column of pillars, and staggered with respect to the first column of pillars, and

a third column of pillars disposed along the first direction and adjacent to the second column of pillars such that the second column of pillars is between the first column of pillars and the third column of pillars, the third column of pillars staggered with respect to the second column of pillars,

wherein a first pitch between a first pillar of the first column and a second pillar of the second column nearest to the first pillar is greater than a second pitch between the second pillar and a third pillar of the third column adjacent to the second pillar, and

wherein the first column of pillars, the second column of pillars, and the third column of pillars are coupled to a same upper selection gate.

2. The semiconductor device of claim 1, wherein the upper selection gate and the cell gates extend along a second direction perpendicular to the first direction when viewed from the top of the semiconductor device, and

wherein the first pillar, the second pillar, and the third pillar are disposed along a third direction when viewed from the top of the semiconductor device, the third direction crossing the first direction and the second direction.

3. The semiconductor device of claim 2, wherein the first direction, the second direction, and the third direction are directions in a same plane.

4. The semiconductor device of claim 1, wherein the first group of pillars include a fourth pillar nearest to the first pillar,

wherein an interval between the first pillar and the fourth pillar is greater than an interval between the first pillar and the second pillar.

5. A semiconductor memory device comprising:

a plurality of horizontal electrodes including an upper selection gate and cell gates below the upper selection gate; and

an array of pillars formed in the plurality of horizontal electrodes, the array of pillars comprising a first column, a second column and a third column disposed adjacent to one another,

wherein each of the first, the second and the third columns comprises pillars disposed along a first direction when viewed from a top of the semiconductor memory device and coupled to a same upper selection gate,

wherein the second column is staggered with the first column and the third column,

wherein a first pitch between a first pillar of the first column and a second pillar of the second column nearest to the first pillar is greater than a second pitch between the second pillar and a third pillar of the third column nearest to the second pillar,

wherein the first pillar, the second pillar, and the third pillar are disposed along a third direction crossing the first direction.

6. The semiconductor device of claim 5, wherein the first group of pillars include a fourth pillar nearest to the first pillar,

wherein an interval between the first pillar and the fourth pillar is greater than an interval between the first pillar and the second pillar.

7. The semiconductor device of claim 5, wherein the upper selection gate and the cell gates extend along a second direction when viewed from the top of the semiconductor device , the second direction being perpendicular to the first direction, and

wherein the first direction, the second direction, and the third direction are directions in a same plane.