Memory cell structure for improving erase speed
First Claim
1. A split-gate flash memory cell, comprising:
- an erase gate and a floating gate laterally spaced over a semiconductor substrate, wherein the floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, a tip defined at an interface of the concave sidewall surface and an upper surface of the floating gate, and an additional sidewall surface on an opposite side of the floating gate as the concave sidewall surface, wherein the concave sidewall surface has a midpoint between a top edge of the concave sidewall surface and a bottom edge of the concave sidewall surface, wherein the top and bottom edges are farther from the additional sidewall surface than the midpoint is, wherein the erase gate has a width-wise bulge at a bottom of the erase gate, wherein the erase gate has a substantially uniform width from a top of the erase gate to a top of the width-wise bulge, and wherein the erase gate has a variable width greater than or equal to the substantially uniform width from the top of the width-wise bulge to a bottom of the erase gate; and
a control gate and a sidewall spacer arranged over the upper surface of the floating gate, wherein the control gate is laterally offset from the tip of the floating gate, and wherein the sidewall spacer is laterally arranged between the control gate and the tip.
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Abstract
A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.
114 Citations
20 Claims
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1. A split-gate flash memory cell, comprising:
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an erase gate and a floating gate laterally spaced over a semiconductor substrate, wherein the floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, a tip defined at an interface of the concave sidewall surface and an upper surface of the floating gate, and an additional sidewall surface on an opposite side of the floating gate as the concave sidewall surface, wherein the concave sidewall surface has a midpoint between a top edge of the concave sidewall surface and a bottom edge of the concave sidewall surface, wherein the top and bottom edges are farther from the additional sidewall surface than the midpoint is, wherein the erase gate has a width-wise bulge at a bottom of the erase gate, wherein the erase gate has a substantially uniform width from a top of the erase gate to a top of the width-wise bulge, and wherein the erase gate has a variable width greater than or equal to the substantially uniform width from the top of the width-wise bulge to a bottom of the erase gate; and a control gate and a sidewall spacer arranged over the upper surface of the floating gate, wherein the control gate is laterally offset from the tip of the floating gate, and wherein the sidewall spacer is laterally arranged between the control gate and the tip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 17, 18)
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8. A split-gate flash memory cell, comprising:
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a shared source/drain region disposed within a semiconductor substrate; an erase gate disposed over the shared source/drain region, wherein the erase gate comprises a pair of convex sidewalls respectively on opposite sides of the erase gate, and further comprises a pair of additional sidewalls respectively on the opposite sides, wherein the additional sidewalls have line-shaped profiles and extend from a top of the erase gate respectively to the convex sidewalls, and wherein the additional sidewalls are laterally between bottom edges respectively of the convex sidewalls; a floating gate disposed over the semiconductor substrate and having a sidewall surface laterally separated from the erase gate by a tunneling dielectric layer, wherein the floating gate has a tip that protrudes outward along the sidewall surface of the floating gate, and wherein the floating gate has another sidewall surface on an opposite side of the floating gate as the sidewall surface; and a control gate separated from the floating gate by a control gate dielectric layer overlying the floating gate; wherein the sidewall surface arcs continuously from a top edge of the sidewall surface to a bottom edge of the sidewall surface, and wherein the sidewall surface has a point laterally spaced between the other sidewall surface and the bottom edge. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A split-gate flash memory cell comprising:
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a semiconductor substrate comprising a first source/drain region and a second source/drain region; an erase gate directly over the second source/drain region, wherein the erase gate bulges along a bottom of the erase gate; a word line and a floating gate laterally spaced between the erase gate and the first source/drain region, wherein the floating gate comprises a first sidewall surface and a second sidewall surface respectively on opposite sides of the floating gate, wherein the second sidewall surface of the floating gate neighbors the erase gate and is concave, and wherein a height of the floating gate increases laterally from the first sidewall surface of the floating gate to the second sidewall surface of the floating gate; and a control gate over the floating gate, wherein a height of the control gate decreases laterally from the first sidewall surface of the floating gate to the second sidewall surface of the floating gate; wherein the erase gate protrudes into the floating gate to a point spaced from and between the first sidewall surface and a bottom edge of the second sidewall surface, wherein the point is defined by a conductive sidewall surface of the erase gate, and wherein the first and second sidewall surfaces of the floating gate are conductive. - View Dependent Claims (15, 16, 19, 20)
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Specification