Devices including gate spacer with gap or void and methods of forming the same

• US 9,917,178 B2
• Filed: 01/30/2017
• Issued: 03/13/2018
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Liu, Chi-Wen, Leung, Ying-Keung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/419,289
• Publication Number:
  US 20170141215A1
• Time in Patent Office: 407 Days
• Field of Search: 438283
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Claims

1. A method comprising:

forming a first inter-layer dielectric layer over a substrate;

forming a gate stack in the first inter-layer dielectric layer and over the substrate;

forming a contact through the first inter-layer dielectric layer to the substrate; and

forming a gate spacer between the gate stack and the contact, the gate spacer being around the gate stack and having a void around the gate stack.

2. The method of claim 1, further comprising:

forming a dummy gate stack over the substrate;

forming a dummy gate spacer around the dummy gate stack, the first inter-layer dielectric layer being formed around the dummy gate spacer;

removing the dummy gate stack to form a first opening, the gate stack being formed in the first opening;

removing at least a portion of the dummy gate spacer to form a second opening around the gate stack; and

conformally depositing a dielectric layer in the second opening, the dielectric layer pinching-off at an upper portion of the second opening, the void being formed within the dielectric layer, at least a portion of the dielectric layer being the gate spacer.

3. The method of claim 1 further comprising:

forming a dummy gate stack over the substrate;

forming a multi-layer gate spacer around the dummy gate stack, the multi-layer gate spacer comprising a first layer extending vertically along one or more sidewall of the dummy gate stack, a second layer extending vertically along the first layer, and a third layer extending vertically along the second layer, the first inter-layer dielectric layer being formed around the multi-layer gate spacer;

removing the dummy gate stack to form a first opening, the gate stack being formed in the first opening;

removing at least a portion of the second layer to form a second opening around the gate stack and between the first layer and the third layer; and

forming a dielectric material in an upper portion of the second opening and between the first layer and the third layer, the void being formed between the first layer and the third layer and below the dielectric material.

4. The method of claim 1, wherein the gate spacer comprises a continuous layer along a first sidewall portion of the gate spacer, a bottom portion of the gate spacer, and a second sidewall portion of the gate spacer, the first sidewall portion contacting the second sidewall portion at an upper portion of the gate spacer, the void being disposed between the first sidewall portion, the bottom portion, and the second sidewall portion.

5. The method of claim 1, wherein the gate spacer comprises a first vertical dielectric layer along one or more sidewall of the gate stack, a second vertical dielectric layer parallel to the first vertical dielectric layer, and a dielectric material disposed between the first vertical dielectric layer and the second vertical dielectric layer, the void being disposed between the first vertical dielectric layer and the second vertical dielectric layer and between the dielectric material and the substrate.

6. The method of claim 1, further comprising:

forming a first dielectric cap over the gate stack; and

forming a second dielectric cap over the contact, and wherein after the forming the gate spacer, top surfaces of the first dielectric cap and the second dielectric cap are co-planar with a top surface of the gate spacer.

7. The method of claim 1, further comprising forming a source/drain region in the substrate, the source/drain region being proximate to the gate stack, the contact connecting to the source/drain region.

8. A method of manufacturing a semiconductor device, the method comprising:

providing a dummy spacer located adjacent to both a gate dielectric and a contact, the gate dielectric being at least partially over a semiconductor fin;

removing at least a portion of the dummy spacer to form a void between the gate dielectric and the contact; and

depositing dielectric material to encapsulate the void between the gate dielectric and the contact.

9. The method of claim 8, wherein the providing the dummy spacer further comprises:

providing a first sub-layer;

providing a dummy second sub-layer adjacent to the first sub-layer; and

providing a third sub-layer adjacent to the dummy second sub-layer.

10. The method of claim 9, wherein the removing at least the portion of the dummy spacer comprises removing at least a portion of the dummy second sub-layer.

11. The method of claim 10, wherein the removing at least the portion of the dummy second sub-layer comprises removing an entirety of the dummy second sub-layer.

12. The method of claim 10, wherein the removing at least the portion of the dummy second sub-layer comprises removing a first portion of the dummy second sub-layer and leaving a second portion of the dummy second sub-layer, the second portion of the dummy second sub-layer having a height less than the semiconductor fin.

13. The method of claim 8, wherein the removing at least a portion of the dummy spacer removes an entirety of the dummy spacer.

14. The method of claim 8, wherein the removing at least a portion of the dummy spacer comprises removing a first portion of the dummy spacer and leaving a second portion of the dummy spacer, the second portion of the dummy spacer having a height less than the semiconductor fin.

15. A method of manufacturing a semiconductor device, the method comprising:

depositing a dielectric layer over a semiconductor substrate with a fin;

forming a gate electrode in the dielectric layer;

forming a contact to the semiconductor substrate;

removing the dielectric layer from a first region between the gate electrode and the contact; and

depositing a dielectric material to form a void within the first region.

16. The method of claim 15, wherein the forming the contact further comprises:

depositing a first interlayer dielectric;

forming an opening in the first interlayer dielectric;

filling the opening with a conductive material; and

recessing the conductive material from a top surface of the first interlayer dielectric.

17. The method of claim 15, wherein the forming the gate electrode further comprises:

forming a capping layer;

forming a work function tuning layer over the capping layer;

forming a barrier layer over the work function tuning layer; and

forming a metal over the barrier layer.

18. The method of claim 15, wherein the depositing the dielectric material is performed at least in part using a conformal deposition process.

19. The method of claim 18, wherein the depositing the dielectric material is performed at least in part with a chemical vapor deposition process.

20. The method of claim 18, wherein the depositing the dielectric material is performed at least in part with an atomic vapor deposition process.