Semiconductor device and method of manufacturing the same

• US 9,917,185 B2
• Filed: 10/28/2016
• Issued: 03/13/2018
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Omori, Kengo
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US15/336,985
• Publication Number:
  US 20170047441A1
• Time in Patent Office: 501 Days
• Field of Search: 257334, 257653, 257654
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Claims

1. A semiconductor device comprising:

a semiconductor layer provided with a gate trench;

a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer for forming part of a side surface of the gate trench;

a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region for forming part of the side surface of the gate trench;

a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region for forming a bottom surface of the gate trench;

a gate insulating film formed on an inner surface of the gate trench; and

a gate electrode embedded inside the gate insulating film in the gate trench, wherein

the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation, a recess portion formed from the surface side in the channel portion such that the recess portion is concaved toward the back surface side of the semiconductor layer with respect to a contact surface between the source region and the channel region and a projection projecting from an end portion of the channel portion toward the back surface of the semiconductor layer in the form of a parabola.

2. The semiconductor device according to claim 1, wherein the projection of the channel region has the same impurity concentration as the channel portion of the channel region.

3. The semiconductor device according to claim 2, wherein the channel portion and the projection have the impurity concentration of 1×

10¹⁷ to 5×

10¹⁷ cm<sup>−

3</sup>.

4. The semiconductor device according to claim 1, wherein the channel portion has a different impurity concentration from a bottom region of the recess portion.

5. The semiconductor device according to claim 1, wherein

the recess portion includes a contact trench passing through the source region from the surface of the semiconductor layer so that the deepest portion reaches the channel region,

the semiconductor layer includes a second conductivity type channel contact region formed on a bottom surface of the contact trench, and

the impurity concentration of the projection is not more than 1/100 of that of the channel contact region.

6. The semiconductor device according to claim 1, wherein

the recess portion includes a contact trench passing through the source region from the surface of the semiconductor layer so that the deepest portion reaches the channel region,

the semiconductor layer includes a second conductivity type channel contact region formed on a bottom surface of the contact trench, and

the projection is formed immediately under the channel contact region.

7. The semiconductor device according to claim 6, wherein

a top portion of the projection immediately under the channel contact region is formed along a position under a central portion in the width direction of the bottom surface of the contact trench.

8. The semiconductor device according to claim 6, wherein

a top portion of the projection immediately under the channel contact region is formed along a position under an end portion in the width direction of the bottom surface of the contact trench.

9. The semiconductor device according to claim 8, wherein

the top portion of the projection includes a plurality of top portions formed in parallel with one another along positions under both end portions in the width direction of the bottom surface of the contact trench.

10. The semiconductor device according to claim 1, wherein

a top portion of the projection is positioned on a side of the bottom surface of the gate trench closer to the back surface of the semiconductor layer.

11. The semiconductor device according to claim 1, wherein

the semiconductor layer consists of an Si semiconductor layer.

12. The semiconductor device according to claim 1, wherein

an end portion of the channel portion is positioned on the surface side of the end portion of the gate trench.

13. The semiconductor device according to claim 7, wherein the projection projects in the form of a parabola such that one top portion of the projection reaches a position under the central portion in the width direction of the bottom surface of the contact trench.

14. The semiconductor device according to claim 8, wherein the projection projects in the form of two parabolas such that top portions of the projection reach positions under a first and a second end portions in the width direction of the bottom surface of the contact trench respectively.

15. The semiconductor device according to claim 14, wherein the respective top portions of the projection parallelly align with each other along the contact trench.

16. The semiconductor device according to claim 15, wherein the top portions are line-symmetrical with respect to a symmetry axis s formed by a perpendicular passing through the central portion in the width direction of the bottom surface of the contact trench.

17. The semiconductor device according to claim 16, wherein an opposite top portion of the channel region located on the symmetry axis s is on a position deeper than the end portion of the gate trench.

18. The semiconductor device according to claim 11, wherein

the Si semiconductor layer includes an Si substrate and an Si epitaxial layer formed on the Si substrate, the Si epitaxial layer having a impurity concentration lower than that of the Si substrate, and

a top portion of the projection is not in contact with the Si substrate.

19. The semiconductor device according to claim 1, wherein the thickness of the channel portion is 0.5 μ

m to 0.9 μ

m and the thickness up to a top portion of the projection is 1.0 μ

m to 1.6 μ

m.

20. The semiconductor device according to claim 1, wherein quantity of projection of the gate trench from an interface between the channel portion and the drain region is 0.2 μ

m to 0.1 μ

m.

21. The semiconductor device according to claim 6, wherein the contact trench has a stripe shape, and

the projection is formed in a stripe shape along the striped contact trench.

22. The semiconductor device according to claim 6, wherein the contact trench is shallower than the gate trench.

23. The semiconductor device according to claim 1, the gate insulating film includes silicon oxide film.