Semiconductor device with control structure including buried portions and method of manufacturing

• US 9,917,186 B2
• Filed: 12/29/2016
• Issued: 03/13/2018
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes, Schulze, Hans-Joachim, Dainese, Matteo, Lechner, Peter, Baburske, Roman
• Primary Examiner(s): WARD, ERIC A
• Application Number:
  US15/394,303
• Publication Number:
  US 20170110574A1
• Time in Patent Office: 439 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8613 : Mesa PN junction diodes

Abstract

A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.

Claims

1. A semiconductor device, comprising:

transistor cells including source zones of a first conductivity type and body zones of a second conductivity type, wherein the source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body; and

control structures that comprise first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa, wherein constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.

2. The semiconductor device of claim 1, wherein the first, second, and third portions are aligned to a bottom plane at a first distance to the first surface.

3. The semiconductor device of claim 1, wherein the control structures comprise at least a first control electrode and a first control dielectric separating the first control electrode from the semiconductor body.

4. The semiconductor device of claim 3, wherein the control dielectric has a first section with a first thickness in a bottom portion averted from the first surface and a second section with a second thickness smaller than the first thickness between the first section and the first surface.

5. The semiconductor device of claim 1, wherein the control structures comprise fourth portions extending into the semiconductor body on further two opposing sides of the semiconductor mesa.

6. The semiconductor device of claim 1, wherein the control structure includes a first control electrode in the second portions, the third portions, and in a bottom section of the first portions, and a second control electrode dielectrically separated from the first control electrode in a top section of the first portion between the first surface and the bottom section.

7. The semiconductor device of claim 1, wherein the semiconductor mesa further comprises further constricted sections between neighboring ones of the second portions.

8. The semiconductor device of claim 1, wherein a width and/or density of the constricted sections varies as a function of a distance between the concerned constricted section and an edge area of the semiconductor body, wherein the edge area is devoid of transistor cells and surrounds a cell field including the transistor cells.

9. A semiconductor device, comprising:

transistor cells comprising source zones of a first conductivity type and body zones of a second conductivity type, wherein the source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body; and

control structures that comprise top portions arranged on two opposing sides of a top section of the semiconductor mesa and extending from a first surface into the semiconductor body, and bottom portions in a distance to the first surface on opposing sides of a bottom section of the semiconductor mesa, wherein the bottom section of the semiconductor mesa is connected to the top section, wherein at least one of the top and bottom sections comprises a variation of an effective width along a horizontal longitudinal extension of the semiconductor mesa and wherein, in case both the top and the bottom sections comprise a variation of an effective width along the horizontal longitudinal extension of the semiconductor mesa variations of an effective width of the bottom section and variations of an effective width of the top section are not geometrically similar.

10. The semiconductor device of claim 9, wherein the bottom portions of the control structures are isolated from each other and are arranged along two parallel lines.

11. The semiconductor device of claim 9, wherein at least one of the top portions of the control structure includes first top portions having a first top width and second top portions having a second top width greater than the first width, the first and second top portions directly adjoining to each other and alternating along the horizontal longitudinal extension of the semiconductor mesa.

12. The semiconductor device of claim 11, wherein the source zones are formed in portions of the semiconductor mesa between opposing first top portions of the two control structures.

13. The semiconductor device of claim 9, wherein the control structure comprises intermediate portions arranged between the top portions and spaced from the top portions of the control structure, a vertical extension of the intermediate portions being smaller than a vertical extension of the top portions of the control structure.

14. The semiconductor device of claim 9, wherein a distance between the top portions of neighboring ones of the control structures is greater than a distance between the bottom portions of neighboring ones of the control structures.