Dynamic clock period modulation scheme for variable charge pump load currents

• US 9,917,507 B2
• Filed: 05/28/2015
• Issued: 03/13/2018
• Est. Priority Date: 05/28/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Reddy, Gooty Sukumar, Kumar, Potnuru Venkata Pradeep, Yadala, Sridhar
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US14/724,067
• Publication Number:
  US 20160352217A1
• Time in Patent Office: 1,020 Days
• Field of Search: 327536, 327589, 327534, 363 74, 331 17, 331 16, 331 34, 331111, 331143, 331183, 331 57
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A charge pump is connected to receive a supply voltage and a clock signal and generate an output voltage. The charge pump is connected to the supply voltage through a transistor whose gate voltage is set by a regulation voltage determined by feedback from the output voltage. The current supplied to the charge pump through this transistor is mirrored in a section that generates the clock signal, where the mirrored current is used by a current controller oscillator. This allows the pump'"'"'s clock frequency to linearly track the load current, improving the pump'"'"'s efficiency.

Claims

1. A charge pump system, comprising:

a charge pump configured to generate an output voltage potential at an output node by use of a clock signal and a supply current; and

a clock circuit configured to produce the clock signal for the charge pump, the clock circuit comprising;

a current mirroring element configured to generate a first current having a magnitude that is substantially a fraction of a magnitude of the supply current to the charge pump, and

a current controlled oscillator configured to produce the clock signal for the charge pump based on the magnitude of the first current such that a frequency of the clock signal varies with the magnitude of the supply current to the charge pump.

2. The charge pump system of claim 1, wherein the current controlled oscillator is configured to vary the frequency of the clock signal substantially linearly with the magnitude of the first current.

3. The charge pump system of claim 1, wherein the current mirroring element includes a first transistor connected between a supply voltage and ground, having a gate connected to receive a regulation voltage, wherein the regulation voltage corresponds to the output voltage potential, and wherein the current controlled oscillator includes:

a current source connected in parallel with the first transistor to provide a second current;

a capacitor;

switching circuitry connected to receive the clock signal and, based on the clock signal, alternately connect the capacitor to charge and discharge at a rate based on the combined first and second currents;

a comparison circuit connected to the capacitor, a first reference voltage, and a second reference voltage, wherein the comparison circuit generates set and reset signals based on a voltage level on the capacitor relative to the first and second reference voltages; and

a latch connected to receive the set and reset signals and generate the clock signal therefrom.

4. The charge pump system of claim 3, wherein the current controlled oscillator further comprises intermediate mirroring circuitry connected to the switching circuitry and through which the first transistor and the current source are connected to ground.

5. The charge pump system of claim 3, further comprising:

a feedback circuit configured to generate the regulation voltage from the output voltage potential; and

a regulation transistor connected between the supply voltage and the charge pump, wherein a gate of the regulation transistor receives the regulation voltage, and wherein the first transistor is sized smaller than the regulation transistor.

6. The charge pump system of claim 1, further comprising regulation circuitry, the regulation circuitry comprising:

a feedback circuit configured to generate a regulation voltage potential corresponding to the output voltage potential, wherein the current mirroring element includes first and second transistors each connected between a supply voltage and ground and each having a gate connected to the regulation voltage potential, and wherein the current controlled oscillator includes;

a set signal generation section having;

a first current source connected in parallel with the first transistor to provide a second current;

a first capacitor;

first switching circuitry connected to receive the clock signal and, based on the clock signal, alternately connect the first capacitor to charge and discharge at a rate based on the combined first and second currents; and

a first comparison circuit connected to the first capacitor and to a reference voltage potential, where the first comparison circuit generates a set signal based on a voltage level on the first capacitor relative to the reference voltage potential; and

a reset signal generation section having;

a second current source connected in parallel with the second transistor to provide a third current;

a second capacitor;

second switching circuitry connected to receive an inverted form of the clock signal and, based on the inverted form of the clock signal, alternately connect the second capacitor to charge and discharge at a rate based on the combined first and third currents; and

a second comparison circuit connected to the second capacitor and to the reference voltage potential, where the second comparison circuit generates a reset signal based on a voltage level on the second capacitor relative to the reference voltage potential; and

a latch connected to receive the set and reset signals and generate the clock signal therefrom.

7. The charge pump system of claim 6, wherein:

the supply current flows to the charge pump through a regulation transistor,

a gate of the regulation transistor is coupled to the reference voltage potential,

the first transistor is sized smaller than the regulation transistor, and

the first and second transistors are similarly sized.

8. The charge pump system of claim 1, further comprising:

a feedback circuit configured to generate a reference voltage signal, wherein the feedback circuit comprises;

a voltage divider circuit connected between the output node and ground, and

an operational amplifier configured to generate the reference voltage signal from a first input connected to a node of the voltage divider circuit, and a second input connected to receive the reference voltage signal; and

a regulation transistor connected between a source voltage and the charge pump, wherein a gate of the regulation transistor receives the reference voltage signal.

9. The charge pump system of claim 1, wherein the charge pump comprises a voltage doubler.

10. The charge pump system of claim 1, wherein the charge pump system is formed on a non-volatile memory circuit.

11. The charge pump system of claim 10, wherein the output voltage potential is for use in one or more of a programming operation, an erase operation, and a sensing operation.

12. The charge pump system of claim 10, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate and that each include a charge storage medium.

13. A method, comprising:

generating an output voltage potential by a charge pump circuit, wherein the charge pump circuit generates the output voltage potential responsive to a pump clock signal and by use of supply current;

mirroring the supply current being supplied to the charge pump circuit to generate the output voltage potential, wherein mirroring the supply current comprises generating a first current, the first current having a level configured to be substantially fractional to a level of the supply current being supplied to the charge pump circuit; and

generating the pump clock signal by use of the first current, wherein generating the pump clock signal comprises adapting a frequency of the pump clock signal based upon the level of the first current such that the frequency of the pump clock signal is dependent upon the level of the supply current being supplied to the charge pump circuit.

14. The method of claim 13, wherein adapting the frequency of the pump clock signal comprises varying the frequency of the pump clock signal linearly with the level of one of the first current and the supply current.

15. The method of claim 13, wherein the supply current is supplied to the charge pump circuit through a first transistor, the method further comprising:

producing a regulation signal configured to correspond to the output voltage potential generated by the charge pump circuit;

applying the regulation signal to a control gate of the first transistor; and

applying the regulation signal to a control gate of a second transistor, the second transistor configured to mirror the supply current being supplied to the charge pump circuit.

16. The method of claim 13, further comprising:

generating a regulation voltage that corresponds to the output voltage potential being generated by the charge pump circuit;

wherein the first current is generated by a current mirror element, comprising first and second transistors connected between a supply voltage and ground and each having a gate connected to receive the regulation voltage; and

wherein the pump clock signal is generated by a current controlled oscillator comprising;

a set signal generation section having;

a first current source connected in parallel with the second transistor to provide a second current;

a first capacitor;

first switching circuitry connected to receive the pump clock signal and, based on the pump clock signal, alternately connect the first capacitor to charge and discharge at a rate based on the combined first and second currents; and

a first comparison circuit connected to the first capacitor and to a reference voltage, where the first comparison circuit generates a set signal based on a voltage level on the first capacitor relative to the reference voltage; and

a reset signal generation section having;

a second current source connected in parallel with the second transistor to provide a third current;

a second capacitor;

second switching circuitry connected to receive an inverted form of the pump clock signal and, based on the inverted form of the pump clock signal, alternately connect the second capacitor to charge and discharge at a rate based on the combined first and third currents; and

a second comparison circuit connected to the second capacitor and to the reference voltage, wherein the second comparison circuit generates a reset signal based on a voltage level on the second capacitor relative to the reference voltage; and

a latch connected to receive the set and reset signals and generate the pump clock signal therefrom.

17. The method of claim 13, wherein the supply current is supplied to the charge pump circuit through a first transistor, the method further comprising:

generating a regulation voltage signal from the output voltage potential; and

applying the regulation voltage signal to a control gate of a first transistor;

wherein the regulation voltage signal is generated by use of a feedback circuit, comprising;

a voltage divider circuit connected between an output node of the charge pump circuit and ground; and

an operational amplifier configured to output the regulation voltage signal, the operational amplifier having a first input connected to a node of the voltage divider circuit and a second input connected to receive a reference voltage signal.

18. The method of claim 13, wherein the method is performed by a charge pump system formed on a non-volatile memory circuit.

19. The method of claim 18, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate and that each include a charge storage medium.

20. A system, comprising:

means for mirroring a supply current to a charge pump, the charge pump configured to generate an output voltage potential on an output node by use of the supply current and a clock signal, wherein mirroring the supply current comprises generating a mirrored supply current having a magnitude that is a fraction of a magnitude of the supply current to the charge pump; and

means for producing the clock signal for the charge pump using the mirrored supply current, wherein a frequency of the clock signal corresponds to the magnitude of the mirrored supply current such that the frequency of the clock signal varies with the magnitude of the supply current to the charge pump.

21. The system of claim 20, wherein the supply current is supplied to the charge pump through a first transistor, and wherein a gate of the first transistor is controlled by a regulation signal, the system further comprising:

means for generating the regulation signal, wherein the regulation signal corresponds to the output voltage potential.