Digital signal up-converting apparatus and related digital signal up-converting method

• US 9,917,586 B2
• Filed: 06/02/2017
• Issued: 03/13/2018
• Est. Priority Date: 05/21/2013
• Status: Active Grant

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Yang-Chuan, Wang, Chi-Hsueh, Chang, Hsiang-Hui, Lin, Bo-Yu
• Primary Examiner(s): Ali, Shawkat M
• Application Number:
  US15/611,822
• Publication Number:
  US 20170272074A1
• Time in Patent Office: 284 Days
• CPC Class Codes: G01R 21/06 by measuring current and voltage G01R21/08 - G01R21/133 take precedence
• CPC Class Codes: G01R 23/00 Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/24 in discharge-tube amplifiers
• CPC Class Codes: H03F 2203/21154 An output signal of a power amplifier being controlled by controlling voltage signal
• CPC Class Codes: H03F 3/2178 using more than one switch or switching amplifier in parallel or in series H03F3/2173, H03F3/2175 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0408 with power amplifiers
• CPC Class Codes: H04B 2001/045 with means for improving efficiency
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/2053 using more than one carrier, e.g. carriers with different phases
• CPC Class Codes: H04L 27/2067 with more than two phase states H04L27/2064 takes precedence
• CPC Class Codes: H04L 27/3411 reducing the peak to average power ratio or the mean power of the constellation; Arrangements for increasing the shape gain of a signal set
• CPC Class Codes: H04L 27/3444 by applying a certain rotation to regular constellations
• CPC Class Codes: H04L 7/0037 : Delay of clock signal
• CPC Class Codes: H04L 7/0091 : Transmitter details
• CPC Class Codes: H04W 24/02 : Arrangements for optimising operational condition

Abstract

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Claims

1. A digital signal up-converting apparatus, comprising:

a clock generating circuit, arranged to generate a reference clock signal;

an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a plurality of second clock signals according to the reference clock signal;

a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit generates a digital output signal according to the first clock signal; and

a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the plurality of second clock signals and the digital output signal, wherein the plurality of second clock signals are non-overlapping;

wherein the sampling circuit samples the digital output signal based on at least one of the plurality of second clock signals and then combines the sampled digital output signal in order to generate a combined digital signal, and

wherein the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal.

2. The digital signal up-converting apparatus of claim 1, wherein the clock generating circuit is arranged to generate a plurality of reference clock signals.

3. The digital signal up-converting apparatus of claim 2, wherein the plurality of reference clock signals comprises at least four reference clock signals.

4. The digital signal up-converting apparatus of claim 1, wherein the adjusting circuit is arranged to generate a plurality of first clock signals and the baseband circuit generates the digital output signal according to the plurality of first clock signals.

5. The digital signal up-converting apparatus of claim 4, wherein the plurality of first clock signals comprises at least four first clock signals.

6. The digital signal up-converting apparatus of claim 1, wherein the plurality of second clock signals comprises at least four second clock signals.

7. The digital signal up-converting apparatus of claim 1, wherein the digital output signal comprises a plurality of digital output signals.

8. The digital signal up-converting apparatus of claim 7, wherein the plurality of digital output signals comprises at least four digital output signals.

9. The digital signal up-converting apparatus of claim 1, further comprising an amplifier, arranged to generate an amplified output signal according to the combined digital signal.

10. The digital signal up-converting apparatus of claim 1, wherein the adjusting circuit comprises a phase adjusting circuit arranged to adjust a phase of the reference clock signal to generate the first clock signal.

11. The digital signal up-converting apparatus of claim 1, wherein the adjusting circuit comprises a duty cycle adjusting circuit arranged to adjust a duty cycle of the reference clock signal to generate the plurality of second clock signals.

12. The digital signal up-converting apparatus of claim 1, wherein the baseband circuit is arranged to delay baseband data to generate the digital output signal according to the first clock signal.

13. The digital signal up-converting apparatus of claim 1, wherein signal edges of the plurality of second clock signals are non-overlapping.

14. A method, comprising:

generating a reference clock signal;

generating a first clock signal and a plurality of second clock signals according to the reference clock signal;

generating digital output signals according to the first clock signal; and

sampling the digital output signals based on at least one of the plurality of second clock signals; and

combining the sampled digital output signals to generate a combined digital signal,

wherein the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal.

15. The method of claim 14, further comprising generating an amplified output signal according to the combined digital signal.

16. The method of claim 14, further comprising adjusting a phase of the reference clock signal to generate the first clock signal.

17. The method of claim 14, further comprising adjusting a duty cycle of the reference clock signal to generate the plurality of second clock signals.

18. The method of claim 14, further comprising delaying baseband data to generate the digital output signals according to the first clock signal.

19. The method of claim 14, wherein signal edges of the plurality of second clock signals are non-overlapping.

20. The method of claim 14, wherein the plurality of second clock signals comprises at least four second clock signals.