Fast voltage level shifter circuit

• US 9,917,587 B2
• Filed: 12/22/2016
• Issued: 03/13/2018
• Est. Priority Date: 01/27/2010
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Gazit, Meir
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US15/388,816
• Publication Number:
  US 20170104487A1
• Time in Patent Office: 446 Days
• Field of Search: 327333, 326 80, 326 81
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Claims

1. A circuit comprising:

a first circuit portion comprising a first switch and a resistor and configured to produce, responsive to an input voltage to a control input of the first switch, an output voltage by passing current through the resistor and the first switch;

a second circuit portion comprising a second switch and configured to draw, responsive to a control input of the second switch, the current through the first switch and the resistor; and

a third circuit portion comprising a charge storage device and configured to discharge into the control input of the second switch, responsive to the input voltage, a charge stored in the charge storage device, wherein the third circuit portion is configured to control the second circuit portion to decrease, in response to the input voltage being unchanged, the current through the first switch and the resistor.

2. The circuit of claim 1, wherein the third circuit portion is configured to control the second circuit portion to increase, in response to a change in the input voltage, the current through the first switch and the resistor.

3. The circuit of claim 1, wherein the first circuit portion comprises a level shifting circuit.

4. The circuit of claim 1, wherein the second circuit portion comprises a current mirror circuit.

5. The circuit of claim 1, wherein the charge storage device is connected to the input voltage via an inverting amplifier, and wherein the control input of the first switch is configured to receive the input voltage without inversion.

6. The circuit of claim 1, wherein each of the first switch and the second switch is selected from a group consisting of:

a silicon controlled rectifier (SCR), an insulated gate bipolar junction transistor (IGBT), a bipolar junction transistor (BJT), a field effect transistor (FET), a junction field effect transistor (JFET), a switching diode, an electrical relay, a reed relay, a solid state relay, an insulated gate field effect transistor (IGFET), a diode for alternating current (DIAC), and a triode for alternating current TRIAC.

7. The circuit of claim 1, wherein the first circuit portion is connected between a voltage source and the second circuit portion, and wherein the second circuit portion is connected between the first circuit portion and ground.

8. A circuit comprising:

a first switch having a control input connected to a first node, wherein the first switch is further connected between a second node and a third node;

a current-controlled source connected to the third node and comprising a control input connected to a fourth node; and

a charge storage circuit connected between the first node and comprising a control input connected to the fourth node, wherein the charge storage circuit is configured to control the current-controlled source to increase, in response to a change in voltage at the first node, a current through the first switch between the second node and the third node, wherein the charge storage circuit is further configured to control the current-controlled source to increase the current by discharging a stored charge into the fourth node.

9. The circuit of claim 8, wherein the charge storage circuit is further configured to control the current-controlled source to decrease, in response to the voltage at the first node being unchanged, the current through the first switch between the second node and the third node.

10. The circuit of claim 8, wherein the charge storage circuit comprises a first capacitor and a second capacitor, the circuit further comprising:

a first inverting amplifier comprising an input connected to the first node and comprising an output connected to the first capacitor; and

a second inverting amplifier comprising an input connected to the output of the first inverting amplifier and comprising an output connected to the second capacitor.

11. The circuit of claim 8, further comprising an inverting amplifier and a second switch, wherein the control input of the first switch is directly connected to the first node and a control input of the second switch is connected to the first node via the inverting amplifier, wherein the second switch is further connected between a fifth node and the third node.

12. The circuit of claim 8, wherein the first switch is selected from a group consisting of:

a silicon controlled rectifier (SCR), an insulated gate bipolar junction transistor (IGBT), a bipolar junction transistor (BJT), a field effect transistor (FET), a junction field effect transistor (JFET), a switching diode, an electrical relay, a reed relay, a solid state relay, an insulated gate field effect transistor (IGFET), a diode for alternating current (DIAC), and a triode for alternating current TRIAC.

13. The circuit of claim 8, wherein the second node is connected between a voltage source and the first switch, and wherein the current-controlled source is connected between the third node and ground.

14. The circuit of claim 8, further comprising a first voltage output node connected to the second node via a diode and a second voltage output node connected to the second node via a resistor.

15. A circuit comprising:

a first circuit portion comprising a first switch and a resistor and configured to produce, responsive to an input voltage to a control input of the first switch, an output voltage by passing current through the resistor and the first switch;

a current mirror comprising a second switch and configured to draw, responsive to a control input of the second switch, the current through the first switch and the resistor; and

a second circuit portion comprising a charge storage device and configured to discharge into the control input of the second switch, responsive to the input voltage, a charge stored in the charge storage device.

16. The circuit of claim 15, wherein the second circuit portion is configured to control the current mirror to increase, in response to a change in the input voltage, the current through the first switch and the resistor.

17. The circuit of claim 15, wherein the second circuit portion is configured to control the current mirror to decrease, in response to the input voltage being unchanged, the current through the first switch and the resistor.

18. The circuit of claim 15, wherein the first circuit portion comprises a level shifting circuit.

19. The circuit of claim 15, wherein the charge storage device is connected to the input voltage via an inverting amplifier, and wherein the control input of the first switch is configured to receive the input voltage without inversion.

20. The circuit of claim 15, wherein the first circuit portion is connected between a voltage source and the current mirror, and wherein the current mirror is connected between the first circuit portion and ground.