Multilevel driver for high speed chip-to-chip communications

• US 9,917,711 B2
• Filed: 01/09/2017
• Issued: 03/13/2018
• Est. Priority Date: 06/25/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Ulrich, Roger
• Primary Examiner(s): Flores, Leon
• Application Number:
  US15/402,148
• Publication Number:
  US 20170118048A1
• Time in Patent Office: 428 Days
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04L 25/03133 with a non-recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

Transmission line driver systems are described which are comprised of multiple paralleled driver elements. The paralleled structure allows efficient generation of multiple output signal levels with adjustable output amplitude, optionally including Finite Impulse Response signal shaping and skew pre-compensation.

Claims

1. An apparatus comprising:

a plurality of driver slices arranged in parallel, each driver slice having a digital driver input and a slice output, each driver slice configured to generate a signal at a signal level determined by the digital driver input, and wherein each driver slice comprises;

a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and

,

for each resistive element, a voltage switching circuit connected to the second end of the resistive element, the voltage switching circuit configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit being controlled by the digital driver input; and

,

a common output node connected to (i) the plurality of driver slice outputs, (ii) a wire of a multi-wire bus.

2. The apparatus of claim 1, further comprising a disabling circuit configured to adjust an output impedance at the common output node by selectively enabling and disabling driver slices in the plurality of driver slices.

3. The apparatus of claim 1, wherein each driver slice further comprising a pre-driver switching circuit configured to couple the respective digital driver input to one of a group of driver input sources.

4. The apparatus of claim 3, wherein the group of driver input sources comprises a quiescent input.

5. The apparatus of claim 1, wherein each driver slice is configured to provide one of at least three possible signal level values to the common output node.

6. The apparatus of claim 1, wherein each resistive element in the plurality of resistive elements has the same impedance value.

7. The apparatus of claim 1, wherein at least two resistive elements for two different driver slices have different impedance values.

8. The apparatus of claim 1, wherein the plurality of driver slices comprises at least forty driver slices.

9. The apparatus of claim 1, wherein an output impedance at the common output node is equal to 6,000 ohms.

10. The apparatus of claim 1, wherein the wire of the multi-wire bus is configured to provide a symbol of a codeword of a vector signaling code, the symbol generated by a summation of the signals generated by the plurality of driver slices.

11. A method comprising:

obtaining an input stream of symbol values;

providing the input stream of symbol values to a plurality of driver slices, each driver slice having a respective resistive element;

generating a plurality of series of signal levels determined by the input stream of symbol values, each respective series of signal level values generated using a respective driver slice, wherein generating the respective series of signal levels comprises selectively coupling the respective resistive element to a constant-voltage node of a respective group of constant-voltage nodes, the constant-voltage node selected based on the input stream of symbol values; and

forming an output symbol value based on a summation of the plurality of series of signal levels at a common output node.

12. The method of claim 11, further comprising adjusting an output impedance at the common output node by selectively enabling and disabling driver slices in the plurality of driver slices.

13. The method of claim 11, wherein for each driver slice, the input stream of symbol values is obtained from a respective pre-driver switching circuit, the input stream of symbol values selected from a group of driver input sources.

14. The method of claim 13, wherein the group of driver input sources comprises a quiescent input.

15. The method of claim 11, wherein each signal level in a given series of signal levels has a signal level value from a set of at least three possible signal level values.

16. The method of claim 11, wherein the resistive element in each driver slice has the same impedance value.

17. The method of claim 11, wherein at least two resistive elements for two different driver slices have different impedance values.

18. The method of claim 11, wherein the plurality of driver slices comprises at least forty driver slices.

19. The method of claim 11, wherein an output impedance at the common output node is equal to 6,000 ohms.

20. The method of claim 11, wherein the output symbol is a symbol of a codeword of a vector signaling code.