Redundant backup using non-volatile memory

• US 9,921,762 B2
• Filed: 09/17/2014
• Issued: 03/20/2018
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Amidi, Mike Hossein, Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott H., Bhakta, Jayesh
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/489,281
• Publication Number:
  US 20150248249A1
• Time in Patent Office: 1,280 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1612 where the redundant component is persistent storage
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Claims

1. A memory system comprising:

a host interface couplable to a host computer;

a circuit coupled to the host interface by way of a data bus and an address and control (addr/cont) bus, the circuit operable to receive data from and deliver data to the host computer based on addr/cont signals received from the host computer;

a volatile memory subsystem coupled to the circuit by way of a first data bus and a first addr/cont bus;

a controller coupled to the circuit by way of a second data bus and a second addr/cont bus;

a voltage monitor circuit coupled to the controller, the voltage monitor circuit operable to monitor a voltage supplied by the host computer via the host interface and to provide a control signal to the controller in response to sensing one or more of a low voltage condition, an imminent power interruption, a power failure, a power reduction, or when power is restored; and

a non-volatile memory subsystem coupled to the controller by way of first and second channels, the non-volatile memory subsystem including (i) a first set of one or more non-volatile memory elements coupled to the first channel, and (ii) a second set of one or more non-volatile memory elements coupled to the second channel, the controller operable to communicate data, status and control information between the host and the non-volatile memory system by way of the host interface,

wherein, in response to the control signal received from the voltage monitor circuit, the controller is operable to (i) receive data from the volatile memory subsystem by way of the circuit, (ii) write a first copy of the received data from the volatile memory subsystem into the first set of one or more non-volatile memory elements using the first channel, and (iii) write a second copy of the data into the second set of one or more non-volatile memory elements using the second channel.

2. The memory system of claim 1, wherein the controller includes a buffer to store the data received from the circuit.

3. The memory system of claim 2, wherein the controller is operable to (i) read the first copy of the data stored in the first set of one or more non-volatile memory elements, (ii) read the second copy of the data stored in the second set of one or more non-volatile memory elements, (iii) determine if the read first copy or the read second copy is invalid based on a comparison with the data stored in the buffer, and (iv) re-write the data stored in the buffer of the controller into the first or second set of one or more non-volatile memory elements from where the invalid first or second copy was read.

4. The memory system of claim 3, wherein the controller is operable to re-write the data stored in the buffer of the controller into a selected location of the first or second set of one or more non-volatile memory elements, and wherein the selected location is a location from where the invalid first or second copy was read or a different location.

5. The memory system of claim 1, wherein, during a data request, the controller is operable to (i) read a first copy of the requested data from a first selected location of the first set of one or more non-volatile memory elements using the first channel, and to repair the first copy if it includes correctable errors, (ii) read a second copy of the requested data from a second selected location of the second set of one or more non-volatile memory elements using the second channel, and repair the second copy if it includes correctable errors, and (iii) provide an error-free copy of the requested data to the circuit.

6. The memory system of claim 5, wherein, if one of the first or second copies includes a block of data with uncorrectable errors, the controller is operable to replace the block of data that includes uncorrectable errors with a valid block of data from the other of the first or second copies, and to repair the first copy or the second copy to generate an error-free copy of the requested data.

7. A memory system comprising:

a host interface couplable to a host computer;

a first non-volatile memory subsystem coupled to a first channel, the first non-volatile memory subsystem including a first set of one or more non-volatile memory elements;

a second non-volatile memory subsystem coupled to a second channel, the second non-volatile memory subsystem including a second set of one or more non-volatile memory elements; and

a controller coupled to the host interface by way of a data bus and an address and control (addr/cont) bus, the controller operable to receive data from and deliver data to the host computer via the data bus based on addr/cont signals received from the host computer via the addr/cont bus, the controller coupled to the first non-volatile memory subsystem by way of the first channel and to the second non-volatile memory subsystem by way of the second channel,

wherein, in response to a data read request from the host computer, the controller is operable to;

(i) read a first copy of the requested data from a first selected location of the first set of one or more non-volatile memory elements through the first channel, determine if the first copy contains a correctable error, and generate an error-free first copy of the requested data by repairing the first copy of the requested data if it contains a correctable error,

(ii) read a second copy of the requested data from a second selected location of the second set of one or more non-volatile memory elements through the second channel, determine if the second copy contains a correctable error, generate an error-free second copy of the requested data by repairing the second copy of the requested data if the second copy of the requested data contains a correctable error, and replace the second copy of the requested data with the error-free first copy of the requested data if the second copy of the requested data contains an uncorrectable error, and

(iii) transmit to the host computer an error-free copy of the requested data corresponding to the first or second error-free copy.

8. The memory system of claim 7, wherein the controller is further operable to notify the host computer with an uncorrectable error message if at least one of the first or second copies of the requested data contains an uncorrectable error.

9. The memory system of claim 8, wherein the controller is further operable to deliver at least one of the first or second copies of the requested data containing an uncorrectable error to the host computer.

10. The memory system of claim 7, wherein said replacing the second copy of the requested data with the error-free first copy of the requested data if the second copy of the requested data contains uncorrectable errors includes writing the error-free first copy into a location of the second set of one or more non-volatile memory elements through the second channel.

11. The memory system of claim 10, wherein the location of the second set of one or more non-volatile memory elements is (a) a location from where the block of data with uncorrectable errors was read, or (b) a different location within the second set of one or more non-volatile memory elements.

12. The memory system of claim 11, wherein the location from where the second copy of the requested data was read is marked as bad block.

13. The memory system of claim 7, further comprising:

a volatile memory subsystem coupled to the controller, wherein the volatile memory subsystem is used to store at least one of the first or second error-free copies.

14. The memory system of claim 7, further comprising:

a volatile memory subsystem coupled to the controller, the volatile memory subsystem including first and second buffers, wherein (i) the first buffer is used to store one or more of the first copy of the requested data and the error-free first copy, and (ii) the second buffer is used to store one or more of the second copy of the requested data and the error-free second copy.

15. The memory system of claim 7, further comprising:

a voltage monitor circuit coupled to the controller, the voltage monitor circuit operable to (i) monitor a supply voltage provided by the host computer via the host interface and (ii) generate a control signal in response to a detected change in the monitored supply voltage, wherein the controller initiates a data read request in response to the control signal.

16. The memory system of claim 7, wherein the controller is further operable to notify the host computer with an uncorrectable error message if both the first and second copies of the requested data contain an uncorrectable error.

17. The memory system of claim 7, wherein the controller determines if the first or second copy contains a correctable error based on ECC (error-correcting code).

18. A memory system comprising:

a host interface couplable to a host computer;

a first non-volatile memory subsystem coupled to a first channel, the first non-volatile memory subsystem including a first set of one or more non-volatile memory elements;

a second non-volatile memory subsystem coupled to a second channel, the second non-volatile memory subsystem including a second set of one or more non-volatile memory elements;

a voltage monitor circuit couplable to the controller, the voltage monitor circuit operable to (i) monitor a supply voltage provided by the host computer via the host interface, and (ii) generate a control signal in response to a detected change in the monitored supply voltage;

a controller coupled to the host interface by way of a data bus and an address and control (addr/cont) bus, the controller operable to receive data from and deliver data to the host computer based on addr/cont signals received from the host computer, the controller coupled to the first non-volatile memory subsystem by way of the first channel and to the second non-volatile memory subsystem by way of the second channel, wherein the controller initiates a data read request in response to the control signal; and

a volatile memory subsystem coupled to the controller, wherein, in response to the data read request, the controller is operable to (i) read a first copy of the requested data from a first selected location of the first set of one or more non-volatile memory elements using the first channel, determine if the first copy contains correctable errors, and repair the first copy if it includes correctable errors, (ii) read a second copy of the requested data from a second selected location of the second set of one or more non-volatile memory elements using the second channel, determine if the second copy contains correctable errors, and repair the second copy if it includes correctable errors, and (iii) provide an error-free copy of the requested data, corresponding to the repaired first or second copy, to the volatile memory subsystem.

19. The memory system of claim 18, wherein the controller is further operable to (i) determine if one of the first or second copies includes a block of data with uncorrectable errors, (ii) replace the block of data with uncorrectable errors with a valid block of data from the other of the first or second copies, and (iii) repair the first copy or the second copy using the valid block.

20. The memory system of claim 18, wherein the controller includes a buffer to store one or more of 1) the first copy of the requested data, 2) the second copy of the requested data, 3) the repaired first copy, and 4) the repaired second copy.

21. The memory system of claim 18, wherein the voltage monitor circuit generates the control signal in response to sensing one or more of a low voltage condition, an imminent power interruption, a power failure, a power reduction, or when power is restored.

22. The memory system of claim 18, wherein the controller determines if the first or second copy contains a correctable error based on ECC (error-correcting code).