Prefetching of discontiguous storage locations in anticipation of transactional execution

• US 9,921,834 B2
• Filed: 02/15/2017
• Issued: 03/20/2018
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Greiner, Dan F., Gschwind, Michael Karl, Michael, Maged M., Salapura, Valentina, Schwarz, Eric M., Slegel, Timothy J.
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US15/432,976
• Publication Number:
  US 20170161070A1
• Time in Patent Office: 398 Days
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.

Claims

1. A computer implemented method for prefetching data at discontiguous storage locations, the method comprising:

executing a prefetch instruction, the prefetch instruction specifying a list having a plurality of entries, each entry specifying a storage address of a block of data and corresponding metadata, the metadata indicating any one of usage of the block of data and information about the list, the executing comprising;

a) obtaining, by a computer system, a plurality of addresses from the plurality of entries of the lists specified by the prefetch instruction; and

b) initiating prefetching to cache lines of a cache the blocks of data corresponding to the obtained plurality of addresses.

2. The method of claim 1, further comprising:

executing a transaction in a multi-processor transactional execution (TX) environment, the transaction having memory operands corresponding to said prefetched blocks of data.

3. The method of claim 1, further comprising:

obtaining the list from any one of a memory location specified by the prefetch instruction, a contiguous range of general registers and a contiguous range of vector registers.

4. The method of claim 3, wherein the prefetch instruction specifies the list through one or more levels of indirection.

5. The method of claim 1, wherein the metadata indicates the usage of the block of data, the indicated usage comprising any one of instruction, data operand, load data, store data, changed data and transaction execution (TX) usage.

6. The method of claim 1, wherein the metadata indicates the information about the list, the indicated information about the list comprising size of the block of data and addressing mode for fetching the block of data.

7. A computer system for prefetching data at discontiguous storage locations, the computer system comprising:

a memory; and

a processor in communications with the memory, wherein the computer system is configured to perform a method, the method comprising;

executing a prefetch instruction, the prefetch instruction specifying a list having a plurality of entries, each entry specifying a storage address of a block of data and corresponding metadata, the metadata indicating any one of usage of the block of data and information about the list, the executing comprising;

a) obtaining, by a computer system, a plurality of addresses from the plurality of entries of the lists specified by the prefetch instruction; and

b) initiating prefetching to cache lines of a cache, the blocks of data corresponding to the obtained plurality of addresses.

8. The computer system of claim 7, wherein the method further comprises executing a transaction in a multi-processor transactional execution (TX) environment, the transaction having memory operands corresponding to said prefetched blocks of data.

9. The computer system of claim 7, wherein the method further comprises obtaining the list from any one of a memory location specified by the prefetch instruction, a contiguous range of general registers and a contiguous range of vector registers.

10. The computer system of claim 9, wherein the prefetch instruction specifies the list through one or more levels of indirection.

11. The computer system of claim 7, wherein the metadata indicates the usage of the block of data, the indicated usage comprising any one of instruction, data operand, load data, store data, changed data and transaction execution (TX) usage.

12. The computer system of claim 7, wherein the metadata indicates the information about the list, the indicated information about the list comprising size of the block of data and addressing mode for fetching the block of data.

13. The computer system of claim 12, wherein the addressing mode comprises an address-space control (ASC) value.

14. The computer system of claim 7, wherein the fetching to the cache is only performed based on the block of data not being in a cache of a cache subsystem comprising a local cache.

15. The computer system of claim 7, wherein the method further comprises using the metadata to set usage information in the cache line associated with the fetched block of data.

16. A computer program product for prefetching data at discontiguous storage locations, the computer program product comprising:

a computer readable storage medium readable by a processor and storing instructions for execution by the processor for performing a method, the method comprising;

executing a prefetch instruction, by the processor, the prefetch instruction specifying a list having a plurality of entries, each entry specifying a storage address of a block of data and corresponding metadata, the metadata indicating any one of usage of the block of data and information about the list, the executing comprising;

a) obtaining, by the processor, a plurality of addresses from the plurality of entries of the lists specified by the prefetch instruction; and

b) initiating, by the processor, prefetching to cache lines of a cache the blocks of data corresponding to the obtained plurality of addresses.

17. The computer program product of claim 16, wherein the method further comprises executing a transaction in a multi-processor transactional execution (TX) environment, the transaction having memory operands corresponding to said prefetched blocks of data.

18. The computer program product of claim 16, wherein the method further comprises obtaining the list from any one of a memory location specified by the prefetch instruction, a contiguous range of general registers and a contiguous range of vector registers.

19. The computer program product of claim 18, wherein the prefetch instruction specifies the list through one or more levels of indirection.

20. The computer program product of claim 16, wherein the metadata indicates the usage of the block of data, the indicated usage comprising any one of instruction, data operand, load data, store data, changed data and transaction execution (TX) usage.