Address expansion and contraction in a multithreading computer system

• US 9,921,848 B2
• Filed: 03/27/2014
• Issued: 03/20/2018
• Est. Priority Date: 03/27/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Busaba, Fadi Y., Farrell, Mark S., Gainey, Jr., Charles W., Greiner, Dan F., Heller, Lisa Cranton, Kubala, Jeffrey P., Osisek, Damian L., Schmidt, Donald W., Slegel, Timothy J.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US14/226,947
• Publication Number:
  US 20150277921A1
• Time in Patent Office: 1,454 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

Claims

1. A computer system, comprising:

a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core; and

a multithreading facility configured to control utilization of the configuration to perform a method comprising;

accessing the primary thread in the ST mode using a core address value;

switching from the ST mode to the MT mode;

forming an expanded address value as a shifted core address value by shifting the core address value by an amount based on a requested maximum thread identifier and concatenating the shifted core address value with a thread address value;

accessing the primary thread or one of the one or more secondary threads in the MT mode using the expanded address value;

switching between the MT mode and the ST mode;

selecting the core address value to access the primary thread based on the core being in the ST mode; and

selecting the expanded address value to access the primary thread or one of the one or more secondary threads based on the core being in the MT mode.

2. The computer system according to claim 1, wherein a standard-format address is used in the ST mode, and the core reverts from the MT mode to the ST mode based on disabling the MT mode.

3. The computer system according to claim 2, wherein only the primary thread and not the one or more secondary threads is accessible based on disabling the MT mode.

4. A computer program product for address adjustment in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising;

accessing the primary thread in the ST mode using a core address value;

switching from the ST mode to the MT mode;

forming an expanded address value as a shifted core address value by shifting the core address value by an amount based on a requested maximum thread identifier and concatenating the shifted core address value with a thread address value;

accessing the primary thread or one of the one or more secondary threads in the MT mode using the expanded address value;

switching between the MT mode and the ST mode;

selecting the core address value to access the primary thread based on the core being in the ST mode; and

selecting the expanded address value to access the primary thread or one of the one or more secondary threads based on the core being in the MT mode.

5. The computer program product according to claim 4, wherein a standard-format address is used in the ST mode, and the core reverts from the MT mode to the ST mode based on disabling the MT mode, and only the primary thread and not the one or more secondary threads is accessible based on disabling the MT mode.