Performing a repair operation in arrays

• US 9,921,906 B2
• Filed: 06/07/2016
• Issued: 03/20/2018
• Est. Priority Date: 01/12/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Koch, Gerrit, Recktenwald, Martin
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/175,285
• Publication Number:
  US 20170199782A1
• Time in Patent Office: 651 Days
• Field of Search: 714764, 714763, 714773, 714 25, 714 54, 714710, 714718, 714723
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A method for performing a repair operation in a computer system using arrays having array cells includes detecting an error in an array. In response to detecting the error, error information is written to an error trap register. The error information includes error data and associated error detection information and a position in an array row. The error information is read from the error trap register and a corresponding data copy is determined and fetched in the computer system. One or more exact bit positions that caused the error are determined by comparing the error data with the corresponding data copy. The array cells which are associated with the determined one or more bit positions are disabled.

Claims

1. A method for performing a repair operation in a computer system using arrays having array cells, the method comprising:

detecting an error in an array;

in response to detecting the error, writing error information to an error trap register, wherein the error information comprise error data and associated error detection information and a position in an array row;

reading the error information from the error trap register;

determining and fetching a corresponding data copy in the computer system for the read error information, wherein the corresponding data copy is a known good data copy of a data that includes the error and wherein the corresponding data copy is obtained from a different level cache than a location that includes the error;

determining one or more bit positions that caused the error by comparing the error data with the corresponding data copy; and

disabling those of the array cells which correspond to the determined one or more bit positions, wherein the disabling comprises reconfiguring the array to use redundant bits instead of the one or more bit positions and wherein the reconfiguring only prevents the use of the one or more bit positions.

2. The method according to claim 1, wherein the computer system comprises a processor cache hierarchy, wherein a hierarchy level is implemented using cache arrays, the cache arrays having cache cells, the method further comprising:

detecting an error in the cache array;

in response to detecting the error, writing error information to the error trap register, wherein the error information comprises at least the error data and associated error detection information and a position in a cache array row;

reading the error information from the error trap register;

determining and fetching a corresponding data copy in another processor cache hierarchy level for the read error information;

determining one or more exact bit positions that caused the error by comparing the error data with the corresponding data copy; and

disabling those of the cache array cells which are associated with the determined one or more bit positions.

3. The method according to claim 1, further comprising indicating an error based on detecting single bit differences by determining one or more exact bit positions that caused the error by comparing the error data with the corresponding data copy.

4. The method according to claim 1, further comprising indicating an error based on detecting multiple bit differences by determining one or more exact bit positions that caused the error by comparing the error data with the corresponding data copy.

5. The method according to claim 1, further comprising providing parity data as associated error detection information.

6. The method according to claim 5, further comprising determining one or more exact bit positions that caused the error by comparing the error data and the corresponding parity data with the corresponding data copy and the corresponding parity data.

7. The method according to claim 1, further comprising performing a repair operation for arrays protected by a scheme that does not include a means to directly determine a fail in one of the one or more bit position.

8. The method according to claim 1, wherein the error trap register comprises information about an access of the array.

9. The method according to claim 1, wherein the error trap register comprises information about a position of an access of the array.

10. The method according to claim 1, further comprising performing the repair operation based on an error indication lying below a predetermined threshold of bit differences and continuing normal operation based on the error indication not lying below the predetermined threshold of bit difference.

11. The method according to claim 1, further comprising performing the repair operation based on an error indication lying below a predetermined threshold of bit differences and continuing normal operation based on an error indication not lying below a predetermined threshold of bit differences.

12. The method according to claim 1, further comprising performing the repair operation by one or both of a hardware state machine and firmware control.

13. The method according to claim 1, further comprising remembering an error position by storing information of detected errors by firmware in a database on known hardware failures.