Demote instruction for relinquishing cache line ownership

• US 9,921,965 B2
• Filed: 01/07/2017
• Issued: 03/20/2018
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shum, Chung-Lung Kevin, Jackson, Kathryn Marie, Webb, Charles Franklin
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US15/400,973
• Publication Number:
  US 20170116120A1
• Time in Patent Office: 437 Days
• Field of Search: 711141, 711146, 711145, 711121
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Claims

1. A computer implemented method for relinquishing, by a selected processor, the selected processor'"'"'s own exclusive ownership of a specified cache line, the selected processor configured to be a processor of a multi-processor system, each processor of the multi-processor system having a respective private cache, the method comprising:

executing, by the selected processor, a demote instruction of a software program, the demote instruction specifying an address of a specified cache line, the executing the demote instruction by the selected processor comprising;

based on the computer system determining that the specified cache line in the selected private cache is exclusively owned by the selected processor, the executing the demote instruction, by the selected processor, causing the selected processor'"'"'s exclusive ownership of the cache line in the selected private cache to be relinquished.

2. The computer implemented method according to claim 1, wherein each processor of the multi-processor system is configured to obtain exclusive ownership of cache lines of the multi-processor system.

3. The computer implemented method according to claim 2, wherein the multi-processor comprises a plurality of private caches, each private cache associated with a respective processor of the multi-processor system, wherein the specified cache line is in a private cache associated with the selected processor.

4. The computer implemented method according to claim 3, wherein execution of the demote instruction, by the selected processor, performs no architectural update.

5. The computer implemented method according to claim 1, further comprising, based on the address being a logical address, translating, by the selected processor, the logical address to a cache address.

6. The computer implemented method according to claim 5, wherein the cache address of the specified cache line is an absolute address of the specified cache line.

7. The computer implemented method according to claim 1, wherein, based on the executing the demote instruction, by the selected processor, the selected processor completes all pending stores to the specified cache line before relinquishing the exclusive ownership of the cache line.

8. The computer implemented method according to claim 1, wherein based on the demote instruction being in an incorrectly predicted branch path of the selected processor, the ownership of the specified cache line is not relinquished by the selected processor.

9. The computer implemented method according to claim 1, wherein based on an instruction, older than the demote instruction not successfully completing, the ownership of the specified cache line is not relinquished by the selected processor.

10. The computer implemented method according to claim 1, wherein the relinquishing the exclusive ownership of the specified cache line, by the selected processor, comprises setting, by the selected processor, the ownership of the specified cache line of the selected cache to any one of shared and read-only.

11. The computer implemented method according to claim 1, wherein the relinquishing the exclusive ownership of the specified cache line, by the selected processor, comprises allowing another processor of the multi-processor system to immediately be given exclusive ownership to the specified cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement.