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Receiver unit for an RF tag

  • US 9,922,214 B2
  • Filed: 03/30/2016
  • Issued: 03/20/2018
  • Est. Priority Date: 04/13/2015
  • Status: Active Grant
First Claim
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1. A receiver unit for a radio frequency (RF) tag, comprising:

  • a first input terminal and a second input terminal each being connected to an antenna;

    a communication stage configured to demodulate and/or to modulate incoming signal in the communication stage; and

    a power stage comprising a voltage converter circuit being configured to supply power to the receiver unit, and a regulation circuit being configured to limit an output voltage of the voltage converter circuit,wherein the regulation circuit comprises a regulator circuit being configured to determine a first current value and a second current value, the second current value being a current value provided in addition to the first current value, and, if the second current value exceeds a predetermined threshold value, to supply a control signal to a limiter circuit configured to limit an input voltage of the voltage converter circuit,wherein the voltage converter circuit includes, at input thereof, an earth generator including a first N-type metal-oxide-semiconductor (MOS) transistor and a second N-type MOS transistor connected to each other such that respective sources thereof are connected to each other to fort a ground of the voltage converter circuit,wherein a drain of the first N-type MOS transistor is connected to the first input terminal and to a gate of the second N-type MOS transistor,wherein a drain of the second N-type MOS transistor is connected to the second input terminal and to a gate of the first N-type MOS transistor,wherein the voltage converter circuit further comprises a plurality of identical structures configured to form a voltage modifier part, andwherein the voltage converter circuit includes, at output thereof, two N-type MOS transistors, where respective sources thereof are connected to each other and are configured to form an output line, a drain of one of the two N-type MOS transistors being connected to a last one of the plurality of identical structures forming the voltage modifier part and extending from the first input terminal, a drain of the other one of the two N-type MOS transistors being connected to the last one of the plurality of identical structures forming the voltage modifier part and extending from the second input terminal, and a respective gate of each of the two N-type MOS transistors being connected to a respective source thereof.

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