Emission electrode scanning circuit, array substrate and display apparatus

• US 9,922,589 B2
• Filed: 10/30/2014
• Issued: 03/20/2018
• Est. Priority Date: 07/04/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Tan, Wen, Qi, Xiaojing
• Primary Examiner(s): McLoone, Peter D
• Application Number:
  US14/764,316
• Publication Number:
  US 20160300523A1
• Time in Patent Office: 1,237 Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers

Abstract

There provide an emission electrode scanning circuit, an array substrate and a display apparatus. The emission electrode scanning circuit includes a plurality of sub scanning circuits connected in cascades, each of which includes a shift register unit, a scanning signal generation unit and a driving output unit. Each sub scanning circuit provides a driving signal to the emission electrode respectively, thereby avoiding bringing in a plurality of driving signal lines from outside of the array substrate. And the plurality of sub scanning circuits shares the emission electrode driving signal line and needs an input of only one start signal to drive the emission electrode scanning circuit to send the emission electrode driving signal progressively. The emission electrode scanning circuit is suitable to be integrated in the seal region of the array substrate, without setting the Fan-out having numerous input lines, which is advantageous for implementing the narrow frame of the display apparatus and also avoids crosstalk produced between the input lines and the gate voltage lines.

Claims

1. An emission electrode scanning circuit comprising a plurality of sub scanning circuits connected in cascades which have identical structures, each of which comprises:

a shift register unit configured to shift a received start signal to obtain a start signal of a next stage of sub scanning circuit and an emission electrode driving control signal, and output the start signal of the next stage of sub scanning circuit to a shift register unit of the next stage of sub scanning circuit;

a scanning signal generation unit connected to an emission electrode driving signal line and an output of the shift register unit, and configured to generate an emission electrode scanning signal according to only these two received signals, the emission electrode driving control signal received from the shift register unit and an emission electrode driving signal received from the emission electrode driving signal line; and

a driving output unit configured to receive the emission electrode scanning signal from the scanning signal generation unit, convert a high level of a received emission electrode scanning signal into an emission electrode driving high level, convert a low level of the emission electrode scanning signal into an emission electrode driving low level, and output them to an emission electrode,

wherein each of the plurality of sub scanning circuits provides a driving signal to the emission electrode respectively, and the plurality of sub scanning circuits shares the emission electrode driving signal line and needs only an input of one start signal to drive the emission electrode scanning circuit to send the emission electrode driving signal progressively.

2. The emission electrode scanning circuit according to claim 1, wherein the shift register unit is further configured to output an inverse signal of the emission electrode driving control signal to the scanning signal generation unit;

the scanning signal generation unit comprises five thin film transistors, wherein a first thin film transistor and a second thin film transistor are P channel type thin film transistors, and a third thin film transistor, a fourth thin film transistor and a fifth thin film transistor are N channel type thin film transistors; and

gates of the first thin film transistor and the fifth thin film transistor are connected to the inverse signal of the emission electrode driving control signal;

a source of the first thin film transistor is connected to a bias high level, and a drain thereof is connected to a source of the second thin film transistor; and

a source of the fifth thin film transistor is connected to an output terminal of the scanning signal generation unit, and a drain thereof is connected to a bias low level;

gates of the second thin film transistor and the fourth thin film transistor are connected to the emission electrode driving signal line;

a drain of the second thin film transistor is connected to the output terminal of the scanning signal generation unit; and

a source of the fourth thin film transistor is connected to the bias low level, and a drain thereof is connected to a source of the third thin film transistor; and

a gate of the third thin film transistor is connected to the emission electrode driving control signal, and a drain thereof is connected to the output terminal of the scanning signal generation unit.

3. The emission electrode scanning circuit according to claim 2, wherein the driving output unit comprises sixth, seventh, eighth, and ninth thin film transistors, wherein the sixth thin film transistor and the eighth thin film transistor are two P channel type thin film transistors, and the seventh thin film transistor and the ninth thin film transistor are N channel type thin film transistors;

and

gates of the sixth thin film transistor and the seventh thin film transistor are connected to the output terminal of the scanning signal generation unit;

a source of the sixth thin film transistor is connected to the driving high level, and a drain thereof is connected to a drain of the seventh thin film transistor; and

a source of the seventh thin film transistor is connected to the driving low level; and

gates of the eighth thin film transistor and the ninth thin film transistor are connected to a drain of the seventh thin film transistor;

a source of the eighth thin film transistor is connected to the driving high level, and a drain thereof is connected to the emission electrode; and

a source of the ninth thin film transistor is connected to the bias low level, and a drain thereof is connected to the emission electrode.

4. The emission electrode scanning circuit according to claim 2, wherein the driving output unit comprises two transfer gates,

wherein a positive control terminal of a first transfer gate and a negative control terminal of a second transfer gate are connected to the emission electrode scanning signal;

the negative control terminal of the first transfer gate and the positive control terminal of the second transfer gate are connected to an inverse signal of the emission electrode scanning signal; and

output terminals of the first transfer gate and the second transfer gate are connected to the emission electrode;

a voltage input terminal of the first transfer gate is connected to the emission electrode driving low level, and a voltage input terminal of the second transfer gate is connected to the emission electrode driving high level.

5. The emission electrode scanning circuit according to claim 1, wherein

the shift register unit is further configured to output the inverse signal of the emission electrode driving control signal to the scanning signal generation unit;

the scanning signal generation unit comprises five thin film transistors, wherein a first thin film transistor and a second thin film transistor are P channel type thin film transistors, and a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor are N channel type thin film transistors; and

gates of the first thin film transistor and the third thin film transistor are connected to the emission electrode driving signal line;

a source of the first thin film transistor is connected to a bias high level, and a drain thereof is connected to a source of the second thin film transistor; and

a source of the third thin film transistor is connected to a source of the fourth thin film transistor, and a drain thereof is connected to an output terminal of the scanning signal generation unit;

gates of the second thin film transistor and the fifth thin film transistor are connected to the inverse signal of the emission electrode driving control signal;

a drain of the second thin film transistor is connected to the output terminal of the scanning signal generation unit; and

a source of the fifth thin film transistor is connected to the bias low level, and a drain thereof is connected to the output terminal of the scanning signal generation unit; and

a gate of the fourth thin film transistor is connected to the emission electrode driving control signal, and a source thereof is connected to the bias low level.

6. The emission electrode scanning circuit according to claim 5, wherein the driving output unit comprises sixth, seventh, eighth, and ninth thin film transistors, wherein the sixth thin film transistor and the eighth thin film transistor are two P channel type thin film transistors, and the seventh thin film transistor and the ninth thin film transistor are N channel type thin film transistors;

and

gates of the sixth thin film transistor and the seventh thin film transistor are connected to the output terminal of the scanning signal generation unit;

a source of the sixth thin film transistor is connected to the driving high level, and a drain thereof is connected to a drain of the seventh thin film transistor; and

a source of the seventh thin film transistor is connected to the driving low level; and

gates of the eighth thin film transistor and the ninth thin film transistor are connected to a drain of the seventh thin film transistor;

a source of the eighth thin film transistor is connected to the driving high level, and a drain thereof is connected to the emission electrode; and

a source of the ninth thin film transistor is connected to the bias low level, and a drain thereof is connected to the emission electrode.

7. The emission electrode scanning circuit according to claim 1, wherein

the scanning signal generation unit comprises a not-and gate and an inverter;

one input terminal of the not-and gate is connected to the emission electrode driving signal line, and the other input terminal thereof is connected to the emission electrode driving control signal, and an output terminal thereof is connected to an input terminal of the inverter; and

an output terminal of the inverter is connected to the output terminal of the scanning signal generation unit.

8. The emission electrode scanning circuit according to claim 1, wherein the driving output unit comprises two transfer gates,

wherein a positive control terminal of a first transfer gate and a negative control terminal of a second transfer gate are connected to the emission electrode scanning signal;

the negative control terminal of the first transfer gate and the positive control terminal of the second transfer gate are connected to an inverse signal of the emission electrode scanning signal; and

output terminals of the first transfer gate and the second transfer gate are connected to the emission electrode;

a voltage input terminal of the first transfer gate is connected to the emission electrode driving low level, and a voltage input terminal of the second transfer gate is connected to the emission electrode driving high level.

9. An array substrate, comprising the emission electrode scanning circuit according to claim 1.

10. The array substrate according to claim 9, wherein the emission electrode scanning circuit is integrated in a seal region of the array substrate.

11. The array substrate according to claim 9, wherein common electrodes of multiple rows of pixels of the array substrate constitute one row of emission electrodes.

12. A display apparatus, comprising the array substrate according to claim 9.

13. The display apparatus according to claim 12, wherein the emission electrode scanning circuit is integrated in a seal region of the array substrate.

14. The display apparatus according to claim 12, wherein common electrodes of multiple rows of pixels of the array substrate constitute one row of emission electrodes.

15. The array substrate according to claim 9, wherein the shift register unit is further configured to output an inverse signal of the emission electrode driving control signal to the scanning signal generation unit;

the scanning signal generation unit comprises five thin film transistors, wherein a first thin film transistor and a second thin film transistor are P channel type thin film transistors, and a third thin film transistor, a fourth thin film transistor and a fifth thin film transistor are N channel type thin film transistors; and

gates of the first thin film transistor and the fifth thin film transistor are connected to the inverse signal of the emission electrode driving control signal;

a source of the first thin film transistor is connected to a bias high level, and a drain thereof is connected to a source of the second thin film transistor; and

a source of the fifth thin film transistor is connected to an output terminal of the scanning signal generation unit, and a drain thereof is connected to a bias low level;

gates of the second thin film transistor and the fourth thin film transistor are connected to the emission electrode driving signal line;

a drain of the second thin film transistor is connected to the output terminal of the scanning signal generation unit; and

a source of the fourth thin film transistor is connected to the bias low level, and a drain thereof is connected to a source of the third thin film transistor; and

a gate of the third thin film transistor is connected to the emission electrode driving control signal, and a drain thereof is connected to the output terminal of the scanning signal generation unit.

16. The array substrate according to claim 15, wherein the driving output unit comprises sixth, seventh, eighth, and ninth thin film transistors, wherein the sixth thin film transistor and the eighth thin film transistor are two P channel type thin film transistors, and the seventh thin film transistor and the ninth thin film transistor are N channel type thin film transistors;

and

gates of the sixth thin film transistor and the seventh thin film transistor are connected to the output terminal of the scanning signal generation unit;

a source of the sixth thin film transistor is connected to the driving high level, and a drain thereof is connected to a drain of the seventh thin film transistor; and

a source of the seventh thin film transistor is connected to the driving low level; and

gates of the eighth thin film transistor and the ninth thin film transistor are connected to a drain of the seventh thin film transistor;

a source of the eighth thin film transistor is connected to the driving high level, and a drain thereof is connected to the emission electrode; and

a source of the ninth thin film transistor is connected to the bias low level, and a drain thereof is connected to the emission electrode.

17. The array substrate according to claim 9, wherein

the shift register unit is further configured to output the inverse signal of the emission electrode driving control signal to the scanning signal generation unit;

the scanning signal generation unit comprises five thin film transistors, wherein a first thin film transistor and a second thin film transistor are P channel type thin film transistors, and a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor are N channel type thin film transistors; and

gates of the first thin film transistor and the third thin film transistor are connected to the emission electrode driving signal line;

a source of the first thin film transistor is connected to a bias high level, and a drain thereof is connected to a source of the second thin film transistor; and

a source of the third thin film transistor is connected to a source of the fourth thin film transistor, and a drain thereof is connected to an output terminal of the scanning signal generation unit;

gates of the second thin film transistor and the fifth thin film transistor are connected to the inverse signal of the emission electrode driving control signal;

a drain of the second thin film transistor is connected to the output terminal of the scanning signal generation unit; and

a source of the fifth thin film transistor is connected to the bias low level, and a drain thereof is connected to the output terminal of the scanning signal generation unit; and

a gate of the fourth thin film transistor is connected to the emission electrode driving control signal, and a source thereof is connected to the bias low level.

18. The array substrate according to claim 17, wherein the driving output unit comprises sixth, seventh, eighth, and ninth thin film transistors, wherein the sixth thin film transistor and the eighth thin film transistor are two P channel type thin film transistors, and the seventh thin film transistor and the ninth thin film transistor are N channel type thin film transistors;

and

gates of the sixth thin film transistor and the seventh thin film transistor are connected to the output terminal of the scanning signal generation unit;

a source of the sixth thin film transistor is connected to the driving high level, and a drain thereof is connected to a drain of the seventh thin film transistor; and

a source of the seventh thin film transistor is connected to the driving low level; and

gates of the eighth thin film transistor and the ninth thin film transistor are connected to a drain of the seventh thin film transistor;

a source of the eighth thin film transistor is connected to the driving high level, and a drain thereof is connected to the emission electrode; and

a source of the ninth thin film transistor is connected to the bias low level, and a drain thereof is connected to the emission electrode.

19. The array substrate according to claim 9, wherein

the scanning signal generation unit comprises a not-and gate and an inverter;

one input terminal of the not-and gate is connected to the emission electrode driving signal line, and the other input terminal thereof is connected to the emission electrode driving control signal, and an output terminal thereof is connected to an input terminal of the inverter; and

an output terminal of the inverter is connected to the output terminal of the scanning signal generation unit.

20. The array substrate according to claim 9, wherein the driving output unit comprises two transfer gates,

wherein a positive control terminal of a first transfer gate and a negative control terminal of a second transfer gate are connected to the emission electrode scanning signal;

the negative control terminal of the first transfer gate and the positive control terminal of the second transfer gate are connected to an inverse signal of the emission electrode scanning signal; and

output terminals of the first transfer gate and the second transfer gate are connected to the emission electrode;

a voltage input terminal of the first transfer gate is connected to the emission electrode driving low level, and a voltage input terminal of the second transfer gate is connected to the emission electrode driving high level.