Source and drain process for FinFET

• US 9,922,816 B2
• Filed: 01/26/2017
• Issued: 03/20/2018
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US15/417,115
• Publication Number:
  US 20170194441A1
• Time in Patent Office: 418 Days
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET includes a fin structure on a substrate; a dielectric layer provided on the fin structure; a metal gate crossing over the dielectric layer; two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the metal gate, each of the two spacers having a length along a direction parallel to a longitudinal axis of the fin structure; and a source and a drain. Each of the source and the drain having a first portion peripherally enclosed by the dielectric layer, and a second portion peripherally enclosed by the two spacers, in which the length of each of the two spacers is greater than a length of the second portion, and a length of a combination of the first portion and the second portion is greater than the length of each of the two spacers.

Claims

1. A method for manufacturing a FinFET, the method comprising:

forming a fin structure on a substrate;

depositing a dielectric layer on the fin structure;

forming a dummy gate crossing over the dielectric layer;

forming two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the dummy gate;

performing a first etching operation on portions of the dielectric layer and the fin structure beside and covered by the two spacers, thereby forming two first recesses respectively peripherally enclosed by the two spacers; and

performing a second etching operation on the fin structure in the first recesses, thereby forming two second recesses peripherally enclosed by the dielectric layer, wherein the second recesses respectively communicate with the first recesses.

2. The method of claim 1, wherein forming the fin structure forms the fin structure from silicon, and an operation of forming the dielectric layer forms the dielectric layer from silicon oxide.

3. The method of claim 1, wherein forming the two spacers forms the two spacers from silicon nitride.

4. The method of claim 1, wherein forming the dummy gate forms the dummy gate from polysilicon.

5. The method of claim 1, further comprising:

performing a wet clean operation on the first recesses and the second recesses after the second etching operation is completed.

6. The method of claim 1, the method further comprising:

performing an epitaxy operation on the substrate to form a source in one of the first recesses and one of the second recesses on the substrate, and to form a drain in the other one of the first recesses and the other one of the second recesses on the substrate after the second etching operation is completed.

7. The method of claim 6, wherein the epitaxy operation forms the source and the drain each of which comprises a silicon germanium (SiGe) layer.

8. The method of claim 6, the method further comprising:

replacing the dummy gate with a metal gate after the epitaxy operation is completed.

9. A method for manufacturing a FinFET, the method comprising:

forming a fin structure on a substrate;

depositing a dielectric layer on a top surface and side surfaces of the fin structure, wherein the fin structure and the dielectric layer are formed from different materials;

forming a dummy gate crossing over the dielectric layer by using a deposition process and an etching process;

forming two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the dummy gate, each of the two spacers having a length along a direction parallel to a longitudinal axis of the fin structure, wherein the two spacers and the fin structure are formed from different materials;

performing one or more etching operations on portions of the dielectric layer and the fin structure beside and covered by the two spacers, thereby forming two recesses peripherally enclosed by the two spacers, the two recesses having a first portion partially enclosed by the dielectric layer and second portion not enclosed by the dielectric layer;

performing a wet clean operation on the two recesses; and

performing an epitaxy operation on the substrate to form a source in one of the two recesses and to form a drain in the other one of the two recesses, thereby forming the source and the drain each of which having a first portion peripherally enclosed by the dielectric layer, and a second portion peripherally enclosed by the two spacers, wherein the length of each of the two spacers is greater than a length of the second portion, and a length of a combination of the first portion and the second portion is greater than the length of each of the two spacers.

10. The method of claim 9, wherein forming the fin structure forms the fin structure from silicon, and forming the dielectric layer forms the dielectric layer from silicon oxide.

11. The method of claim 9, wherein forming the two spacers forms the two spacers from silicon nitride.

12. The method of claim 9, wherein forming the dummy gate forms the dummy gate from polysilicon.

13. The method of claim 9, wherein the epitaxy operation is performed to form the source and the drain each of which comprises a silicon germanium (SiGe) layer.

14. The method of claim 9, wherein forming the fin structure is performed by recessing the substrate.

15. The method of claim 9, the method further comprising:

replacing the dummy gate with a metal gate after the epitaxy operation is completed.

16. A FinFET comprising:

a substrate;

a fin structure on the substrate;

a dielectric layer provided on the fin structure;

a metal gate crossing over the dielectric layer;

two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the metal gate, each of the two spacers having a length along a direction parallel to a longitudinal axis of the fin structure, wherein; and

a source and a drain, each of the source and the drain having a first portion peripherally enclosed by the dielectric layer, and a second portion peripherally enclosed by the two spacers, wherein the length of each of the two spacers is greater than a length of the second portion, and a length of a combination of the first portion and the second portion is greater than the length of each of the two spacers.

17. The FinFET of claim 16, wherein the fin structure is formed from silicon, and the dielectric layer is formed from silicon oxide.

18. The FinFET of claim 16, wherein the two spacers are formed from silicon nitride.

19. The FinFET of claim 16, wherein the source and the drain are formed from silicon germanium.

20. The FinFET of claim 16, wherein each of the source and the drain comprises an epitaxy layer.