Package structure with dummy die

• US 9,922,964 B1
• Filed: 09/19/2016
• Issued: 03/20/2018
• Est. Priority Date: 09/19/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Huang, Li-Hsien
• Primary Examiner(s): Williams, Alexander Oscar
• Application Number:
  US15/268,843
• Publication Number:
  US 20180082987A1
• Time in Patent Office: 547 Days
• Field of Search: 257737, 257738, 257778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A package structure and method for forming the same are provided. The package structure includes a substrate, and a device die formed over the substrate. The device die has a first height. The package structure includes a dummy die formed over the substrate and adjacent to the device die, and the dummy die has a second height. The second height is smaller than the first height. The package structure also includes a package layer formed between the device die and the dummy die.

Claims

1. A package structure, comprising:

a substrate;

a device die formed over the substrate, wherein the device die comprises a device substrate and a conductive pad over the device substrate, and the device substrate has a first height;

a dummy die formed over the substrate and adjacent to the device die, wherein the dummy die comprises a dummy substrate, and the dummy substrate has a second height, the second height is smaller than the first height; and

a package layer formed between the device die and the dummy die.

2. The package structure as claimed in claim 1, further comprising:

a buffer layer formed on the dummy die, wherein a top surface of the buffer layer is lower than a top surface of the device die.

3. The package structure as claimed in claim 1, further comprising:

a through via formed adjacent to the device die, wherein the through via has a third height, the third height is higher than the first height.

4. The package structure as claimed in claim 1, further comprising:

a redistribution structure formed over the package layer, wherein the redistribution structure is electrically connected to the device die.

5. The package structure as claimed in claim 1, wherein a height ratio of the second height to the first height is in a range from about 65% to about 85%.

6. The package structure as claimed in claim 1, wherein a coefficient of thermal expansion (CTE) of the dummy die is substantially identical to a coefficient of thermal expansion (CTE) of the device die.

7. The package structure as claimed in claim 1, further comprising:

a through via formed adjacent to the device die; and

a second package structure formed on the device die, wherein the second package structure is electrically connected to the through via.

8. A package structure, comprising:

a substrate;

a first device die formed over the substrate, wherein the first device die comprises a first device substrate and a conductive pad over the first device substrate, and the first device substrate has a first height;

a first dummy die formed over the substrate and adjacent to the first device die, wherein the first dummy die comprises a first dummy substrate, and the first dummy substrate has a second height, the second height is smaller than the first height;

a first package layer surrounding the first device die and the first dummy die, wherein a top surface of the first dummy die is covered by the first package layer; and

a redistribution structure formed over the first package layer, wherein the redistribution structure is electrically connected to the first device die.

9. The package structure as claimed in claim 8, further comprising:

a through via formed adjacent to the first device die, wherein a top surface of the through via is leveled with a top surface of the first device die.

10. The package structure as claimed in claim 9, further comprising:

a second package structure formed on the device die, wherein the second package structure is electrically connected to the through via.

11. The package structure as claimed in claim 8, further comprising:

an under bump metallurgy (UBM) layer formed on the redistribution structure; and

an electrical connector formed on the UBM layer.

12. The package structure as claimed in claim 8, wherein the first device die has a first height, the first dummy die has a second height, and a height ratio of the second height to the first height is in a range from about 65% to about 85%.

13. The package structure as claimed in claim 8, wherein a coefficient of thermal expansion (CTE) of the first dummy die is the same as a coefficient of thermal expansion (CTE) of the first device die.

14. The package structure as claimed in claim 8, further comprising:

a second device die formed over the package layer; and

a second dummy die formed adjacent to the second device die.

15. The package structure as claimed in claim 14, further comprising:

a second package layer formed between the second device die and the second dummy die, wherein a top surface of the second dummy die is covered by the second package layer.

16. A package structure, comprising:

a first package structure, comprising;

a first device die formed over a substrate;

a first dummy die formed over the substrate;

a first package layer surrounding the first device die and the first dummy die, wherein the first dummy die is covered by the first package layer; and

a redistribution structure formed over the first package layer, wherein the redistribution structure is electrically connected to the first device die; and

a second package structure, comprising;

a second dummy die formed over the redistribution structure; and

a second package layer surrounding the second dummy die, wherein the second dummy die is covered by the second package layer.

17. The package structure as claimed in claim 16, further comprising:

a through via formed adjacent to the first device die, wherein the through via is electrically connected to the redistribution structure.

18. The package structure as claimed in claim 16, wherein the first device die has a first height, the first dummy die has a second height, and the second height is smaller than the first height.

19. The package structure as claimed in claim 16, further comprising:

a buffer layer formed on the first dummy die, wherein the buffer layer is formed between the first dummy die and the first package layer.

20. The package structure as claimed in claim 16, further comprising:

a third package structure formed below the first package structure, wherein the first package structure is formed between the second package structure and the third package structure.