Three-dimensional memory device containing separately formed drain select transistors and method of making thereof
First Claim
1. A three-dimensional memory device comprising:
- an alternating stack of insulating layers and electrically conductive layers located over a substrate;
at least one drain select level conductive layer located over the alternating stack, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another along a second horizontal direction;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; and
drain select level channel portions vertically extending through the at least one drain select level conductive layer, contacting a respective memory level channel portion, and laterally surrounded by a respective drain select level gate dielectric and a respective one of the electrically conductive line structures at each level of the at least one drain select level conductive layer;
wherein;
the memory stack structures are arranged in rows that extend along the first horizontal direction with a first row-to-row pitch along the second horizontal direction across an area including two or more electrically conductive line structures of a same drain select level;
for each electrically conductive line structure, a respective array of drain select level channel portions extends through the electrically conductive line structure, and drain select level channel portions within the respective array are arranged in at least four rows that extend along the first horizontal direction with a second row-to-row pitch along the second horizontal direction; and
the second row-to-row pitch is less than the first row-to-row pitch.
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Accused Products
Abstract
Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.
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Citations
24 Claims
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1. A three-dimensional memory device comprising:
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an alternating stack of insulating layers and electrically conductive layers located over a substrate; at least one drain select level conductive layer located over the alternating stack, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another along a second horizontal direction; memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; and drain select level channel portions vertically extending through the at least one drain select level conductive layer, contacting a respective memory level channel portion, and laterally surrounded by a respective drain select level gate dielectric and a respective one of the electrically conductive line structures at each level of the at least one drain select level conductive layer; wherein; the memory stack structures are arranged in rows that extend along the first horizontal direction with a first row-to-row pitch along the second horizontal direction across an area including two or more electrically conductive line structures of a same drain select level; for each electrically conductive line structure, a respective array of drain select level channel portions extends through the electrically conductive line structure, and drain select level channel portions within the respective array are arranged in at least four rows that extend along the first horizontal direction with a second row-to-row pitch along the second horizontal direction; and the second row-to-row pitch is less than the first row-to-row pitch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming a three-dimensional memory device, comprising:
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forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced by, electrically conductive layers; forming memory openings through the alternating stack; forming memory stack structures in the memory openings, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; forming at least one drain select level dielectric layer over the alternating stack; forming drain select level openings through the at least one drain select level dielectric layer; forming drain select level lateral recesses by removing portions of the at least one drain select level dielectric layer through the drain select level openings, wherein the drain select level lateral recesses are laterally spaced among one another by electrically insulating line structures that are remaining portions of the at least one drain select level dielectric layer; forming at least one drain select level conductive layer in the drain select level lateral recesses, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another by the electrically insulating line structures along a second horizontal direction; forming drain select level gate dielectrics at a periphery of each of the drain select level openings; and forming drain select level channel portions in remaining volumes of the drain select level openings. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification