Semiconductor device with surface insulating film

• US 9,923,073 B2
• Filed: 02/02/2017
• Issued: 03/20/2018
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/423,112
• Publication Number:
  US 20170148886A1
• Time in Patent Office: 411 Days
• Field of Search: 257 77, 257328, 257330-334
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 : with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4958 : with a multiple layer structure
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion;

a gate trench formed at a surface side of the cell portion;

a gate electrode buried in the gate trench via a gate insulating film; and

a gate finger to make contact with the gate electrode, the gate finger disposed in at least the outer peripheral portion,

wherein the gate trench includes a line-shaped trench that reaches the outer peripheral portion and runs across the gate finger under the gate finger.

2. The semiconductor device according to claim 1, wherein

the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and

the semiconductor device further comprises a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

3. The semiconductor device according to claim 1, further comprising a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, wherein

a first part of the surface insulating film on the cell portion has the same thickness as that of a second part of the surface insulating film on the outer peripheral portion.

4. The semiconductor device according to claim 1, wherein the gate trench includes an inner trench at a portion lateral to which the channel is formed at ON-time, and an outer trench constituted of an extension portion of the inner trench, disposed outside with respect to the inner trench, and

the semiconductor device further includes a second conductivity-type layer formed at side and bottom portions of the outer trench.

5. The semiconductor device according to claim 1, wherein

the gate trench is selectively formed in a region under the gate finger, and

the semiconductor device further comprises a high-concentration layer of a first conductivity type formed in a semiconductor surface of the semiconductor layer where the gate trench is not formed in the region under the gate finger, containing an impurity at a higher concentration than that of the semiconductor layer.

6. The semiconductor device according to claim 1, wherein the cell portion includes:

a source region of a first conductivity type disposed in a manner exposed on a surface of the semiconductor layer;

a channel region of a second conductivity type which is disposed in a manner contacting the source region and in which the channel is formed at ON-time;

a drain region of a first conductivity type disposed in a manner contacting the channel region;

a second trench selectively formed in a source portion defined in a manner including the source region in the surface of the semiconductor layer; and

a channel contact region of a second conductivity type selectively disposed at a bottom portion of the second trench, electrically connected with the channel region.

7. The semiconductor device according to claim 1, wherein the cell portion includes:

a source region of a first conductivity type disposed in a manner exposed on a surface of the semiconductor layer;

a channel region of a second conductivity type which is disposed in a manner contacting the source region and in which the channel is formed at ON-time;

a drain region of a first conductivity type disposed in a manner contacting the channel region;

a second trench selectively formed in a source portion defined in a manner including the source region in the surface of the semiconductor layer;

a trench buried portion buried in the second trench; and

a channel contact region of a second conductivity type selectively disposed at a position higher than that of a bottom portion of the second trench in the source region, electrically connected with the channel region.

8. The semiconductor device according to claim 7, wherein the trench buried portion consists of an insulating film formed on an inner surface of the second trench and a polysilicon layer buried inside of the insulating film.

9. The semiconductor device according to claim 8, wherein the insulating film is made of any of SiO₂, AlON, Al₂O₃, SiO₂/AlON, SiO₂/AlON/SiO₂, SiO₂/SiN, and SiO₂/SiN/SiO₂.

10. The semiconductor device according to claim 8, wherein the insulating film has a SiO₂ film containing nitrogen (N).

11. The semiconductor device according to claim 8, wherein the insulating film is, at the bottom portion of the second trench, formed to be thicker than a part at a side portion of the second trench.

12. The semiconductor device according to claim 8, wherein the polysilicon layer is made of n⁺-type polysilicon.

13. The semiconductor device according to claim 7, wherein the trench buried portion consists of an insulating layer that fills back the second trench.

14. The semiconductor device according to claim 13, wherein the insulating layer is made of SiO₂.

15. The semiconductor device according to claim 14, wherein the insulating layer is made of SiO₂ containing phosphorus (P) or boron (B).

16. The semiconductor device according to claim 7, wherein the trench buried portion consists of a polysilicon layer that fills back the second trench.

17. The semiconductor device according to claim 16, wherein the polysilicon layer is made of p⁺-type polysilicon.

18. The semiconductor device according to claim 6, further comprising a second conductivity-type layer formed at the bottom portion and a side portion of the second trench in a manner continuing from the channel region and the channel contact region.

19. The semiconductor device according to claim 1, wherein the gate electrode includes a base film made of polysilicon formed on an inner surface of the gate trench, and a buried metal containing at least one of Mo, W, Al, Pt, Ni, and Ti buried inside of the base film.

20. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a surface metal layer made of a metal containing copper (Cu) disposed at a surface side of the semiconductor layer.

21. The semiconductor device according to claim 20, wherein the surface metal layer contains an Al—

Cu-based alloy.

22. The semiconductor device according to claim 1, wherein in the cell portion, unit cells defined in a grid shape by the gate trench are formed in plural numbers.

23. The semiconductor device according to claim 1, wherein in the cell portion, unit cells defined in a striped shape by the gate trench are formed in plural numbers.

24. The semiconductor device according to claim 1, wherein the semiconductor layer is made of SiC, GaN, or diamond.

25. The semiconductor device according to claim 3, wherein the first part and the second part of the surface insulating film have thickness of 5500 Å

to 20000 Å

.