DC-DC converters having a half-bridge node, controllers therefor and methods of controlling the same

• US 9,923,471 B2
• Filed: 10/13/2016
• Issued: 03/20/2018
• Est. Priority Date: 10/15/2015
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Degen, Peter Theodorus Johannes, van Elk, Henricus Theodorus Petrus Johannes
• Primary Examiner(s): Laxton, Gary L
• Application Number:
  US15/292,529
• Publication Number:
  US 20170110971A1
• Time in Patent Office: 523 Days
• CPC Class Codes: H02M 1/0006 Arrangements for supplying an adequate voltage to the control circuit of converters
• CPC Class Codes: H02M 1/0035 using burst mode control
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/327 against abnormal temperatures
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 7/4815 Resonant converters H02M7/4811 and H02M7/4826 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

There is disclosed a controller for a DC-DC converter comprising a series arrangement of a high-side switch and low-side switch with a half-bridge node therebetween, the controller comprising a high-side part for driving the high-side switch and configured to be powered, when the low-side switch is open, by a rechargeable power supply connected between the half-bridge node and a power supply node, the high-side part comprising a level shifter, driver, latch part comprising a latch having set and reset inputs and configured to latch the driver to either an on-state or an off-state, and a further circuit, wherein the latch part is configured and adapted to prevent the further circuit from drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state. A DC-DC converter having such a controller is also disclosed, as are methods of operating a converter.

Claims

1. A controller for a DC-DC converter comprising a series arrangement of a high-side switch and low-side switch with a half-bridge node therebetween,

the controller comprising a high-side part for driving the high-side switch and configured to be powered, when the low-side switch is open, by a rechargeable power supply connected between the half-bridge node and a power supply node,

the high-side part comprising a level shifter, a driver, a latch part comprising a latch having a set input and a reset input and configured to latch the driver to either an on-state or an off-state, and a further circuit,

wherein the latch part is configured and adapted to prevent the further circuit from drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state.

2. The controller as claimed in claim 1, wherein the further circuit comprises an undervoltage lock-out circuit which is comprised in the latch part.

3. The controller as claimed in claim 1 wherein the latch further comprises a further reset input, a Q output and a Q-not output.

4. The controller as claimed in claim 2, wherein a further reset input is coupled to an output of the undervoltage lock-out circuit.

5. The controller as claimed in claim 3, wherein the latch comprises a pair of cross-coupled NOR gates, a first one of the pair of NOR gate comprising the set input and the Q-not output, and a second one of the pair of NOR gates comprising the reset input, the further reset input and the Q output.

6. The controller as claimed in claim 2, wherein the undervoltage lock-out circuit comprises a comparator for comparing a threshold voltage difference with a difference between a voltage at the half-bridge node and an inverted version of the Q-not output of the latch part.

7. The controller as claimed in claim 2, wherein the undervoltage lock-out circuit comprises a first MOS transistor having a source connected to the half-bridge node voltage and a drain connected to the power supply node via a biasing resistor, and the latch part is configured and adapted to prevent the biasing resistor drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state.

8. The controller as claimed in claim 7, wherein the comparator output is provided as the gate input to the first MOS transistor, and the undervoltage lock-out circuit is configured to ensure the further reset input is tied to the half-bridge node voltage, by turning on the first MOS transistor, in response to the voltage difference between the half-bridge node voltage and the inverted version of the Q-not outputs of the latch part exceeding a threshold voltage difference.

9. The controller as claimed in claim 7, wherein a comparator comprises a second MOS transistor connected in a source-follower arrangement between the power supply node and the half-bridge node voltage via a resistor, and the source terminal of the second MOS transistor is connected to the gate of the first MOS transistor, such that the threshold voltage difference is a sum of the threshold voltages of the first and second MOS transistors.

10. The controller as claimed in claim 1, wherein the undervoltage lock-out circuit comprises a first MOS transistor having a source connected to the half-bridge node voltage via one or more diodes and a drain connected to the power supply node via a biasing resistor, and the latch part is configured and adapted to prevent the biasing resistor drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state.

11. The controller as claimed in claim 10, wherein an inverted version of the Q-not output is provided as a gate input to the first MOS transistor.

12. A DC-DC converter comprising the controller as claimed in claim 1 and an inductive element.

13. The DC-DC converter as claimed in claim 12, wherein the rechargeable power supply comprises a capacitor arrangement.

14. A method of controlling a DC-DC converter comprising a series arrangement of a high-side switch and low-side switch with a half-bridge node therebetween, and a controller comprising a high-side part for driving the high-side switch, the high-side part comprising a level shifter, a driver, a latch part configured to latch the driver to either an on-state or an off-state, and a further circuit,

the method comprising:

sequentially closing and opening the high-side switch and the low-side switch, alternately,

charging a power supply connected between the half-bridge node and a supply node when the low-side switch is closed;

providing power to the high-side part from the power supply when the low-side switch is open;

and preventing the further circuit from drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state.

15. The method of claim 14, wherein the further circuit is an undervoltage lock-out circuit comprising a series arrangement of an undervoltage lock-out switch and a biasing resistor and the method comprises, in sequence,

closing the low-side switch;

opening the low-side switch;

generating a pulse cur_pulse_on, thereby setting a latch signal slatch high, and activating the undervoltage lock-out circuit;

determining, by means of the undervoltage lockout circuit, whether there is sufficient voltage to operate the high-side switch;

in response to there being sufficient voltage to operate the high-side switch, closing the undervoltage lock-out switch to draw current through the biasing resistor thereby force a further reset input to the latch low; and

in response to there being insufficient voltage to operate the high-side switch, holding the undervoltage lock-out switch open to cause the further reset input to the latch to be high and thereby prevent the high-side switch from operating.