Clock tracking algorithm for twinkle VPPM in optical camera communication systems

• US 9,923,638 B1
• Filed: 12/22/2016
• Issued: 03/20/2018
• Est. Priority Date: 12/22/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Perez-Ramirez, Javier, Roberts, Richard D.
• Primary Examiner(s): Dobson, Daniel
• Application Number:
  US15/388,533
• Time in Patent Office: 453 Days
• CPC Class Codes: H04B 10/112 Line-of-sight transmission over an extended range
• CPC Class Codes: H04B 10/116 Visible light communication
• CPC Class Codes: H04B 10/524 Pulse modulation

Abstract

Optical signaling is implemented by modulating visible light with variable pulse position modulation (VPPM). VPPM is a composite waveform and its optical signal includes a Start Frame Delimiter (SFD) which indicates start of optical signaling. To identify modulated lights, the duty cycle is periodically changed in the waveform to induce an AM envelope at a frequency higher than the response of the human eye. The signal is then sampled via a camera producing an alias frequency that produces noticeable blinking. Because the communication is asynchronous, the desired camera frame rate (f_c) in relationship to the modulation bit rate timing clock (or symbol rate, f_s) is only approximate. Consequently, a frequency offset develops between the camera frame rate (f_c) and the symbol rate (f_s) in transmission of long packets. The disclosed embodiments provide a detection algorithm, system and apparatus to provide clock offset tracking and correction.

Claims

1. A receiver circuitry to correct frequency offset between a receiving camera and a transmitting LED source, comprising:

a shift register to receive incoming data from the LED source, the incoming data having a plurality of symbols and a symbol rate (f_s), the shift register having a plurality of storage cells, each storage cell to receive and store one data bit per clock cycle, each bit of data representing a sampled pixel state and each bit of data sampled at a camera frame rate (f_c);

a plurality of comparator logic gates to correspond to a first group of the shift register storage cells, the plurality of logic gates configured to receive a sampled bit of data from a corresponding shift register storage cell during a clock cycle; and

a controller to receive an output from the first plurality of comparator logic gates to identify a frequency offset between the symbol rate (f_s) and the camera frame rate (f_c) as one of a positive, negative or neutral frequency offset, the controller configured to compensate for the frequency offset if the frequency offset is one of the positive or negative frequency offset.

2. The receiver circuitry of claim 1, wherein the shift register receives and stores data at a long exposure mode and switches to short exposure mode to identify a region of interest (ROI) of modulated light.

3. The receiver circuitry of claim 1, wherein the shift register receives a start frame delimiter (SFD) in the incoming data and synchronizes the camera frame rate (f_c) to the SFD.

4. The receiver circuitry of claim 1, wherein the plurality of comparators logic gates receive multiple sampled data and compare the sampled data with a threshold.

5. The receiver circuitry of claim 1, wherein the controller determines the frequency offset by comparing a sampled bit sequence of a first symbol (S₋

3, S<sub>−

2</sub>, S<sub>−

1</sub>, S₀) of a first bit (B_N) with a predetermined threshold sequence.

6. The receiver circuitry of claim 5, wherein the controller further identifies the bit values for a prior bit (B_N−

1) and a current bit decision (B_N).

7. The receiver circuitry of claim 5, wherein the controller compensates for the negative frequency offset by sampling a subsequent symbol to obtain at least three new data samplings.

8. The receiver circuitry of claim 5, wherein the controller compensates for the positive frequency offset by sampling a subsequent symbol to obtain at least five new data samplings and discarding a first of the five samplings.

9. A tangible machine-readable non-transitory storage medium that contains instructions, which when executed by one or more processors result in performing operations to correct frequency offset between a receiving camera and a transmitting LED source, the instructions comprising:

receiving an incoming light at a pixel array of an optical receiving device;

identifying a modulated light from the incoming light, the modulated light received at region of interest (ROI) of the pixel array, the modulated light carrying a data stream having a plurality of symbols and a symbol rate (f_s);

identifying a start frame delimiter (SFD) in the data stream and sampling the plurality of symbols at a camera frame rate (f_c);

determining a frequency offset between the camera frame rate (f_c) and the symbol rate (f_s) of the data stream;

identifying the frequency offset as one of a positive, negative or neutral and compensating for the frequency offset if the frequency offset is one of the positive or negative frequency offset.

10. The medium of claim 9, wherein the modulated light defines a variable pulse modulation (VPPM) wave to modulate the data stream into a carrier wave.

11. The medium of claim 9, wherein receiving an incoming light at a pixel array further comprises recording the incoming light a long exposure mode and wherein identifying modulated light further comprises switching to short exposure mode.

12. The medium of claim 9, wherein identifying a start frame delimiter further comprises synchronizing the receiving camera frame rate (f_c) to the SFD.

13. The medium of claim 9, wherein determining the frequency offset further comprises comparing a sampled bit sequence (S₋

3, S<sub>−

2</sub>, S<sub>−

1</sub>, S₀) of a first bit (B_N) with a predetermined threshold sequence.

14. The medium of claim 13, wherein determining the frequency offset further comprises identifying the bit values for a prior bit (B_N−

1) and a current bit decision (B_N).

15. The medium of claim 13, further comprising compensating for the negative frequency offset by sampling a subsequent symbol to obtain at least three new data samplings.

16. The medium of claim 13, further comprising compensating for the positive frequency offset by sampling a subsequent symbol to obtain at least five new data samplings and discarding a first of the five samplings.

17. A method to correct frequency offset between a receiving camera and a transmitting LED source, the method comprising:

receiving an incoming light at a pixel array of an optical receiving device;

identifying a modulated light from the incoming light, the modulated light received at region of interest (ROI) of the pixel array, the modulated light carrying a data stream having a plurality of symbols and a symbol rate (f_s);

identifying a start frame delimiter (SFD) in the data stream and sampling the plurality of symbols at a camera frame rate (f_c);

determining a frequency offset between the camera frame rate (f_c) and the symbol rate (f_s) of the data stream;

identifying the frequency offset as one of a positive, negative or neutral and compensating for the frequency offset if the frequency offset is one of the positive or negative frequency offset.

18. The method of claim 17, wherein the modulated light defines a variable pulse modulation (VPPM) wave to modulate the data stream into a carrier wave.

19. The method of claim 17, wherein receiving an incoming light at a pixel array further comprises recording the incoming light a long exposure mode and wherein identifying modulated light further comprises switching to short exposure mode.

20. The method of claim 17, wherein identifying the SFD further comprises synchronizing the camera frame rate (f_c) to the SFD.

21. The method of claim 17, wherein determining the frequency offset further comprises comparing a sampled bit sequence (S₋

3, S<sub>−

2</sub>, S<sub>−

1</sub>, S₀) of a first bit (B_N) with a predetermined threshold sequence.

22. The method of claim 21, wherein determining the frequency offset further comprises identifying the bit values for a prior bit (B_N−

1) and a current bit decision (B_N).

23. The method of claim 21, further comprising compensating for the negative frequency offset by sampling a subsequent symbol to obtain at least three new data samplings.

24. The method of claim 21, further comprising compensating for the positive frequency offset by sampling a subsequent symbol to obtain at least five new data samplings and discarding a first of the five samplings.