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Power-efficient chopper amplifier

  • US 9,924,904 B2
  • Filed: 09/02/2014
  • Issued: 03/27/2018
  • Est. Priority Date: 09/02/2014
  • Status: Active Grant
First Claim
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1. An electrical circuit device for amplifying a physiological signal, the device comprising:

  • a modulation unit configured to receive an input signal generated based on the physiological signal, and to modulate the input signal to produce a modulated signal;

    an amplification and transconductance unit configured to amplify an amplitude of the modulated signal and increase a transconductance of the modulated signal to produce a transconductance enhanced modulated and amplified signal, wherein the amplification and transconductance unit comprises at least a first complementary pair of transistors and a second complementary pair of transistors configured to receive the modulated signal and to amplify and increase the transconductance of the modulated signal; and

    a demodulation unit configured to receive the transconductance enhanced modulated and amplified signal and to demodulate the transconductance enhanced modulated and amplified signal to generate a chopper-stabilized amplified version of the input signal,wherein a gate of a first PMOS transistor of the first complementary pair of transistors is connected to the modulation unit to receive a first differential voltage signal from the modulation unit, and a drain of the first PMOS transistor of the first complementary pair of transistors is connected to the demodulation unit,wherein a gate of a first NMOS transistor of the first complementary pair of transistors is connected to the modulation unit to receive the first differential voltage signal from the modulation unit, and a drain of the first NMOS transistor of the first complementary pair of transistors is connected to the demodulation unit, wherein;

    the drain of the first PMOS transistor is commonly connected to the drain of the first NMOS transistor, andthe voltage at the drain of the first PMOS transistor is substantially equal to the voltage at the drain of the first NMOS transistor throughout a voltage range at the drain of the first PMOS transistor,wherein a gate of a second PMOS transistor of the second complementary pair of transistors is connected to the modulation unit to receive a second differential voltage signal from the modulation unit, and a drain of the second PMOS transistor of the second complementary pair of transistors is connected to the demodulation unit, andwherein a gate of the second NMOS transistor of the second complementary pair of transistors is connected to the modulation unit to receive the second differential voltage signal from the modulation unit, and a drain of the second NMOS transistor of the second complementary pair of transistors is connected to the demodulation unit the demodulation unit, wherein;

    the drain of the second PMOS transistor is commonly connected to the drain of the second NMOS transistor, andthe voltage at the drain of the second PMOS transistor is substantially equal to the voltage at the drain of the second NMOS transistor throughout a voltage range at the drain of the second PMOS transistor.

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