Conditional processor auto boot with no boot loader when coupled with a nonvolatile memory
First Claim
1. A method to start a processor without requiring a boot controller, comprising:
- a) providing the processor configured to execute firmware instructions that it has fetched from a non-volatile memory and an instruction intercept circuit configured to detect an un-programmed non-volatile memory value and to substitute the un-programmed non-volatile memory value by a SLEEP opcode;
b) fetching by the processor from the non-volatile memory a first instruction from a default address PC INIT or from an address stored in a register PC_INIT;
c) checking, if the first instruction of the non-volatile memory is un-programmed or if it is programmed with firmware and, if the first instruction of the non-volatile memory is un-programmed, go to step d), else go to step f);
d) substitute the first instruction by a sleep instruction and stopping code execution by the processor by the sleep instruction until a valid trigger event occurs;
e) programming firmware into the memory with an entry point at the PC_INIT address or loading firmware and associated data into the non-volatile memory from a host interface with a firmware entry point while the processor has stopped execution and, when the loading of the firmware and of the associated data is complete the valid trigger event starts the firmware execution; and
f) executing firmware code directly from the programmed memory without the need of a boot controller.
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Accused Products
Abstract
The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.
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Citations
13 Claims
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1. A method to start a processor without requiring a boot controller, comprising:
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a) providing the processor configured to execute firmware instructions that it has fetched from a non-volatile memory and an instruction intercept circuit configured to detect an un-programmed non-volatile memory value and to substitute the un-programmed non-volatile memory value by a SLEEP opcode; b) fetching by the processor from the non-volatile memory a first instruction from a default address PC INIT or from an address stored in a register PC_INIT; c) checking, if the first instruction of the non-volatile memory is un-programmed or if it is programmed with firmware and, if the first instruction of the non-volatile memory is un-programmed, go to step d), else go to step f); d) substitute the first instruction by a sleep instruction and stopping code execution by the processor by the sleep instruction until a valid trigger event occurs; e) programming firmware into the memory with an entry point at the PC_INIT address or loading firmware and associated data into the non-volatile memory from a host interface with a firmware entry point while the processor has stopped execution and, when the loading of the firmware and of the associated data is complete the valid trigger event starts the firmware execution; and f) executing firmware code directly from the programmed memory without the need of a boot controller. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer system, comprising:
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a) a processor connected to a bus arbiter, wherein the processor is configured to fetch a first instruction of a non-volatile memory and to check upon this value of the first instruction if the first instruction of the non-volatile memory is un-programmed and, if it so, to decode the fetched value to a SLEEP instruction, to enter a stalled state and to resume operation after a trigger indicates that a firmware has been loaded from a host interface into the non-volatile memory or, if the first instruction of the non-volatile memory is programmed with firmware, to execute the firmware directly from the programmed memory without the need of a boot controller; b) said bus arbiter connected to the host interface and to the non-volatile memory; c) said non-volatile memory; d) an instruction intercept circuit placed between the non-volatile memory and the processor configured to detect the un-programmed memory value and then to substitute the un-programmed memory value with the SLEEP opcode before it is decoded by the processor; and e) said host interface configured to load firmware via the bus arbiter to the non-volatile memory, hence programming the non-volatile memory while execution of said processor is halted. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification