Conditional processor auto boot with no boot loader when coupled with a nonvolatile memory

• US 9,928,079 B2
• Filed: 09/23/2014
• Issued: 03/27/2018
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: Dialog Semiconductor UK Ltd (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor UK Ltd (Renesas Electronics Corporation)
• Inventors: Todd, Philip
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): HARRINGTON, CHERI L.
• Application Number:
  US14/493,410
• Publication Number:
  US 20160085559A1
• Time in Patent Office: 1,281 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.

Claims

1. A method to start a processor without requiring a boot controller, comprising:

a) providing the processor configured to execute firmware instructions that it has fetched from a non-volatile memory and an instruction intercept circuit configured to detect an un-programmed non-volatile memory value and to substitute the un-programmed non-volatile memory value by a SLEEP opcode;

b) fetching by the processor from the non-volatile memory a first instruction from a default address PC INIT or from an address stored in a register PC_INIT;

c) checking, if the first instruction of the non-volatile memory is un-programmed or if it is programmed with firmware and, if the first instruction of the non-volatile memory is un-programmed, go to step d), else go to step f);

d) substitute the first instruction by a sleep instruction and stopping code execution by the processor by the sleep instruction until a valid trigger event occurs;

e) programming firmware into the memory with an entry point at the PC_INIT address or loading firmware and associated data into the non-volatile memory from a host interface with a firmware entry point while the processor has stopped execution and, when the loading of the firmware and of the associated data is complete the valid trigger event starts the firmware execution; and

f) executing firmware code directly from the programmed memory without the need of a boot controller.

2. The method of claim 1, wherein the nonvolatile memory comprises EEPROM, FLASH, OTP or other types of non-volatile memories which have a known un-programmed or erased bit value.

3. The method of claim 1, wherein the valid trigger event comprises internal or external interrupts.

4. The method of claim 1, wherein the valid trigger event comprises wakeup triggers.

5. The method of claim 1, wherein the valid trigger event comprises RESET activation wherein the firmware entry point a PC_INITaddress, wherein the RESET activation is followed by forcing a power cycle and triggering execution of the firmware.

6. The method of claim 1, wherein the loading of the firmware is performed into an area of a memory map followed by adapting a program counter to point to the firmware entry point and triggering a wakeup event.

7. The method of claim 1, wherein after the valid trigger event the processor is left in the stalled state and the firmware processing is taken over by an external host with access to a memory map.

8. A computer system, comprising:

a) a processor connected to a bus arbiter, wherein the processor is configured to fetch a first instruction of a non-volatile memory and to check upon this value of the first instruction if the first instruction of the non-volatile memory is un-programmed and, if it so, to decode the fetched value to a SLEEP instruction, to enter a stalled state and to resume operation after a trigger indicates that a firmware has been loaded from a host interface into the non-volatile memory or, if the first instruction of the non-volatile memory is programmed with firmware, to execute the firmware directly from the programmed memory without the need of a boot controller;

b) said bus arbiter connected to the host interface and to the non-volatile memory;

c) said non-volatile memory;

d) an instruction intercept circuit placed between the non-volatile memory and the processor configured to detect the un-programmed memory value and then to substitute the un-programmed memory value with the SLEEP opcode before it is decoded by the processor; and

e) said host interface configured to load firmware via the bus arbiter to the non-volatile memory, hence programming the non-volatile memory while execution of said processor is halted.

9. The computer system of claim 8, wherein said processor reading of said un-programmed non-volatile memory occurs when the processor fetches its first instruction from a default address PC-INIT and if the memory is un-programmed, then a next instruction will be a SLEEP instruction read from the un-programmed non-volatile memory.

10. The computer system of claim 8, wherein said trigger event comprises internal or external interrupts, wakeup triggers, or a RESET activation, which would cause the instruction fetch to start again at the PC_INIT address.

11. The computer system of claim 8, wherein the firmware is a boot program or another initialization program.

12. The computer system of claim 8, wherein the processor is configured to perform said resumption of operation directly from programmed memory without the need of a boot controller.

13. The computer system of claim 8, wherein the instruction intercept circuit comprises:

a comparator having inputs and an output, wherein the comparator is configured to compare a first input comprising data captured from the non-volatile memory with a second input representing the known un-programmed value of the non-volatile memory and the output of the comparator is a first input to a logical AND gate indicating if there is a match between both inputs by a match flag;

said logical AND gate configured to set a first logical value if the match flag is set and a second input of the logical AND gate defining a first instruction flag have a same logical value, wherein an output of the logical AND gate is connected to a multiplexer; and

said multiplexer configured to provide a SLEEP instruction as a first instruction to the processor if the first logical value is set and to pass data read from the non-volatile memory unmodified to be used a first instruction if the first logical value is not set.