Memory system

• US 9,928,138 B2
• Filed: 09/11/2015
• Issued: 03/27/2018
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Nakazumi, Shinichiro, Ueki, Katsuhiko, Kojima, Yoshihisa
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/851,991
• Publication Number:
  US 20160239381A1
• Time in Patent Office: 928 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Claims

1. A memory system comprising:

a memory configured to be written data therein, the memory including a memory cell configured to hold charge of an amount corresponding to a value included in the data, the memory converting an amount of charge held by the memory cell into the value in reading on the basis of comparison between the amount of charge held by the memory cell and a determination potential;

a first correction unit configured to execute error correction; and

a processor configured to execute a first process of reading first data from the memory by making the memory use a first determination potential, execute a second process of reading the first data by making the memory use a second determination potential different from the first determination potential in a case where the first correction unit fails in error correction of the first data read through the first process, and execute a third process of reading second data different from the first data from the memory by making the memory use a third determination potential in a case where the first correction unit succeeds in error correction of the first data read through the second process, the third determination potential being the second determination potential used by the memory through the second process, wherein

the processor stores the second determination potential in the case where the first correction unit succeeds in the error correction of the first data read through the second process, and uses the stored second determination potential as the third determination potential,

the memory includes multiple block groups,

each of the multiple block groups includes one or more blocks,

each of the one or more blocks is a unit of erase and includes a plurality of the memory cells, and

the processor stores the second determination potential for each of the multiple block groups.

2. The memory system according to claim 1, wherein in the case where the first correction unit succeeds in the error correction of the first data read through the second process, the processor stores setting information indicating the third determination potential therein, and makes the memory use the third determination potential in the third process on the basis of the stored setting information.

3. The memory system according to claim 2, wherein when the first correction unit fails in the error correction of the first data read through the second process, the processor changes the second determination potential and executes the second process again.

4. The memory system according to claim 2, wherein the processor executes the second process one or more times, has multiple first setting information, and selects second setting information from the multiple first setting information for each second process, the second setting information being setting information indicating the second determination potential.

5. The memory system according to claim 4, wherein the processor has order information, and selects the second setting information for each second process from the multiple first setting information in an order according to the order information.

6. The memory system according to claim 4, wherein

each of the multiple first setting information is associated with identification information, and

the processor stores identification information associated with third setting information, the third setting information being setting information indicating the third determination potential.

7. The memory system according to claim 4, wherein each of the multiple first setting information is a difference from a fixed value.

8. The memory system according to claim 1, wherein the processor executes refresh of the first data at least on the basis of whether or not the first correction unit fails in the error correction of the first data read through the second process.

9. The memory system according to claim 8, wherein the processor executes the first process periodically.

10. The memory system according to claim 1, further comprising a second correction unit having a higher correction capability than a correction capability of the first correction unit, the second correction unit executing error correction of the first data read through the second process in the case where the first correction unit fails in the error correction of the first data read through the second process.

11. The memory system according to claim 1, wherein the processor executes the second process one or more times, has multiple first setting information, selects second setting information from the multiple first setting information for each second process, and converts the selected second setting information into third setting information, the third setting information being information indicating the second determination potential.

12. The memory system according to claim 11, wherein

the memory includes multiple word lines, and

the processor converts the second setting information into the third setting information on the basis of location information of a word line in which the first data is written.

13. The memory system according to claim 12, wherein the memory is a three-dimensional NAND flash memory including the multiple word lines that are stacked.

14. The memory system according to claim 1, wherein

each of the multiple block groups includes two or more blocks, and

the processor accesses the two or more blocks included in a same block group among the multiple block groups in parallel.

15. The memory system according to claim 14, wherein

the memory includes first and second chips,

the two or more blocks included in the same block group includes a first block and a second block,

the first chip includes the first block, and

the second chip includes the second block.