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Memory system

  • US 9,928,138 B2
  • Filed: 09/11/2015
  • Issued: 03/27/2018
  • Est. Priority Date: 02/17/2015
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a memory configured to be written data therein, the memory including a memory cell configured to hold charge of an amount corresponding to a value included in the data, the memory converting an amount of charge held by the memory cell into the value in reading on the basis of comparison between the amount of charge held by the memory cell and a determination potential;

    a first correction unit configured to execute error correction; and

    a processor configured to execute a first process of reading first data from the memory by making the memory use a first determination potential, execute a second process of reading the first data by making the memory use a second determination potential different from the first determination potential in a case where the first correction unit fails in error correction of the first data read through the first process, and execute a third process of reading second data different from the first data from the memory by making the memory use a third determination potential in a case where the first correction unit succeeds in error correction of the first data read through the second process, the third determination potential being the second determination potential used by the memory through the second process, whereinthe processor stores the second determination potential in the case where the first correction unit succeeds in the error correction of the first data read through the second process, and uses the stored second determination potential as the third determination potential,the memory includes multiple block groups,each of the multiple block groups includes one or more blocks,each of the one or more blocks is a unit of erase and includes a plurality of the memory cells, andthe processor stores the second determination potential for each of the multiple block groups.

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