Systems and methods for last written page handling in a memory device

• US 9,928,139 B2
• Filed: 06/28/2016
• Issued: 03/27/2018
• Est. Priority Date: 02/11/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Chen, Zhengang, Cai, Yu, Haratsch, Erich F., Dong, Zhimin
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US15/195,900
• Publication Number:
  US 20160378598A1
• Time in Patent Office: 637 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/37 Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35

Abstract

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

Claims

1. A system for reading data, the system comprising:

a memory read circuit operable to access a data set from a group of memory cells;

a controller circuit operable to;

determine that the group of memory cells was a last written group of memory cells; and

based at least in part on determining that the group of memory cells was the last written group of memory cells, cause the memory read circuit to re-access the data set from the group of memory cells.

2. The system of claim 1, wherein the memory read circuit accesses the data set using a standard reference value to distinguish bit values in the group of memory cells.

3. The system of claim 1, wherein the memory read circuit re-accesses the data set using a last written reference value to distinguish bit values in the group of memory cells.

4. The system of claim 1, wherein the system further comprises a memory circuit including a superset of memory cells, and wherein the group of memory cells is a subset of the superset of memory cells.

5. The system of claim 4, wherein each of the cells of the superset of memory cells are selected from a group consisting of:

a single bit memory cell, a two-bit memory cell, and a three bit memory cell.

6. The system of claim 4, the system further comprising:

a last written group memory operable to maintain a location of the last written group of memory cells in the superset of memory cells.

7. The system of claim 6, wherein the controller circuit determines that the group of memory cells was the last written group of memory cells based at least in part on a comparison of a read address with the location of the last written group of memory cells accessed from the last written group memory.

8. The system of claim 1, wherein the system further comprises:

a hard decision decoder circuit operable to;

apply a hard decision decode algorithm to the data set from the group of memory cells accessed using a standard reference value to yield a first decode output; and

apply the hard decision decode algorithm to the data set from the group of memory cells accessed using a last written reference value to yield a second decode output.

9. The system of claim 8, wherein the controller circuit determines that the group of memory cells was the last written group of memory cells based at least in part on the occurrence of one or more errors in one of the first decode output or the second decode output.

10. The system of claim 1, wherein the system further comprises:

a soft decision decoder circuit operable to apply a soft decision decode algorithm to a soft read output from the group of memory cells; and

wherein the controller circuit is further operable to;

count a number of applications of the soft decision decode algorithm that have been applied to the data set accessed from the group of memory cells; and

based at least in part on the number of applications, triggering a background task to restore the data set from the group of memory cells.

11. The system of claim 10, wherein the background task includes a data recycle task.

12. The system of claim 4, wherein the controller circuit is further operable to preclude a data write to the superset of memory cells when the controller circuit determines that the group of memory cells was a last written group of memory cells, and until the memory read circuit finishes re-accessing the data set from the group of memory cells to distinguish bit values in the group of memory cells.

13. A method for recovering data from a memory device, the method comprising:

accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells;

determining that the group of memory cells was a last written group of memory cells; and

based at least in part on determining that the group of memory cells was the last written group of memory cells, re-accessing the data set from the group of memory cells.

14. The method of claim 13, wherein the memory device includes a flash memory circuit, the flash memory circuit including a superset of memory cells, and wherein the group of memory cells is a subset of the superset of memory cells.

15. The method of claim 13, wherein re-accessing the data set from the group of memory cells includes using a last written reference value to distinguish the bit values in the group of memory cells.

16. The method of claim 13, wherein the controller circuit determines that the group of memory cells was the last written group of memory cells based at least in part on a comparison of a read address with the location of the last written group of memory cells accessed from the last written group memory.

17. The method of claim 13, wherein the method further comprises:

applying a hard decision decode algorithm to the data set from the group of memory cells accessed using a standard reference value to yield a first decode output; and

applying the hard decision decode algorithm to the data set from the group of memory cells accessed using a last written reference value to yield a second decode output.

18. The method of claim 13, wherein the method further comprises:

applying a soft decision decode algorithm to a soft read output from the group of memory cells;

counting a number of applications of the soft decision decode algorithm that have been applied to the data set accessed from the group of memory cells; and

based at least in part on the number of applications, triggering a background task to restore the data set from the group of memory cells.

19. A flash memory storage system, the system comprising:

a memory read circuit operable to access a data set from a group of flash memory cells;

a controller circuit operable to;

determine that the group of flash memory cells was a last written group of cells; and

based at least in part on determining that the group of flash memory cells was a last written group of cells, causing the memory read circuit to re-access the data set from the group of flash memory cells;

a hard decision decoder circuit operable to;

apply a hard decision decode algorithm to the data set from the group of flash memory cells; and

apply the hard decision decode algorithm to the data set from the group of flash memory cells; and

wherein the controller circuit determines that the group of flash memory cells was the last written group of flash memory cells based at least in part on an occurrence of one or more errors.

20. The system of claim 19, further comprising:

a flash memory circuit including a superset of flash memory cells, wherein the group of flash memory cells is a subset of the superset of flash memory cells;

wherein the memory read circuit accesses the data set from the group of flash memory cells using a standard reference value to distinguish bit values in the group of flash memory cells; and

wherein the memory read circuit re-accesses the data set from the group of flash memory cells using a last written reference value to distinguish the bit values in the group of flash memory cells.