Method and system for improving swap performance

• US 9,928,169 B2
• Filed: 05/07/2014
• Issued: 03/27/2018
• Est. Priority Date: 05/07/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Romanovsky, Leon, Marcu, Alon
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US14/272,238
• Publication Number:
  US 20150324119A1
• Time in Patent Office: 1,420 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. One of the characteristics of SLC memory is that data is written more quickly in the SLC memory than the MLC memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation.

Claims

1. A method for performing a swap operation, the method comprising:

performing in a computing device having a volatile memory and a non-volatile memory, wherein the non-volatile memory has multi-level cell (MLC) memory forming a first swap area and single-level cell (SLC) memory forming a second swap area;

monitoring a rate at which incoming data is being sent to the volatile memory;

when the monitored rate is below a first predetermined threshold, swapping first data from the volatile memory to the first swap area of the non-volatile memory; and

when the monitored rate is above the first predetermined threshold;

swapping the first data from the volatile memory to the second swap area of the non-volatile memory; and

when the monitored rate is below the first predetermined threshold, moving the first data from the second swap area of the non-volatile memory to the first swap area of the non-volatile memory.

2. The method of claim 1, wherein the first and second swap areas are different memory partitions, the SLC memory in the second swap area enabling faster data writes relative to the MLC memory in the first swap area.

3. The method of claim 1, wherein the first and second swap areas are different areas in a single memory partition, wherein the first and second swap areas have different logical block address ranges.

4. The method of claim 1, wherein the first swap area has a logical block address range addressable by a processor in the computing device, and wherein the second swap area is a buffer memory.

5. The method of claim 1 further comprising:

determining whether the computing device is operating in selective burst mode; and

if it is determined that the computing device is operating in selective burst mode, using the second swap area of the non-volatile memory for the swap operation but using other areas of the non-volatile memory for other write operations.

6. The method of claim 1, wherein a write priority assigned to a command determines whether data associated with that command will be written to the first swap area or the second swap area.

7. The method of claim 1, further comprising moving second data from the volatile memory to both the first and second swap areas of the non-volatile memory during a swap operation.

8. The method of claim 1, wherein the non-volatile memory is part of a storage module having a storage controller, and wherein the storage controller determines whether the monitored rate is below or above the first predetermined threshold.

9. The method of claim 1, further comprising copying the first data from the SLC memory in the second swap area into the MLC memory in the first swap area.

10. The method of claim 9, wherein the computing device initiates and controls the copying.

11. The method of claim 9, wherein the non-volatile memory is part of a storage module, which has a storage controller, and wherein the storage controller controls the copying in response to a copy command from the computing device.

12. The method of claim 9, wherein the non-volatile memory is part of a memory die, and wherein the copying is performed as an on-chip copy process on the memory die.

13. The method of claim 1, wherein the computing device is a mobile device.

14. The method of claim 1, wherein the non-volatile memory is part of a storage module, and wherein the storage module is embedded in the computing device.

15. The method of claim 1, wherein the non-volatile memory is part of a storage module, and wherein the storage module is removably connected to the computing device.

16. The method of claim 1, wherein the non-volatile memory has a three-dimensional configuration.

17. A computing device comprising:

a volatile memory;

a non-volatile memory, wherein the non-volatile memory has multi-level cell (MLC) memory forming a first swap area and single-level cell (SLC) memory forming a second swap area; and

a processor in operative communication with the volatile and non-volatile memories, wherein the processor is configured to;

monitor a rate at which incoming data is being sent to the volatile memory;

when the monitored rate is below a first predetermined threshold, swap first data from the volatile memory to the first swap area of the non-volatile memory; and

when the monitored rate is above the first predetermined threshold,

swap the first data from the volatile memory to the second swap area of the non-volatile memory; and

when the monitored rate is below the first predetermined threshold, moving the first data from the second swap area of the non-volatile memory to the first swap area of the non-volatile memory.

18. The computing device of claim 17, wherein the first and second swap areas are different memory partitions, the SLC memory in the second swap area enabling faster data writes relative to the MLC memory in the first swap area.

19. The computing device of claim 17, wherein the first and second swap areas are different areas in a single memory partition, wherein the first and second swap areas have different logical block address ranges.

20. The computing device of claim 17, wherein the first swap area has a logical block address range addressable by a processor in the computing device, and wherein the second swap area is a buffer memory.

21. The computing device of claim 17, wherein the processor is further configured to:

determine whether the computing device is operating in selective burst mode; and

if it is determined that the computing device is operating in selective burst mode, use the second swap area of the non-volatile memory for the swap operation but using other areas of the non-volatile memory for other write operations.

22. The computing device of claim 17, wherein a write priority assigned to a command determines whether data associated with the command will be written to the first swap area or the second swap area.

23. The computing device of claim 17, wherein the processor is further configured to move second data from the volatile memory to both the first and second swap areas of the non-volatile memory during a swap operation.

24. The computing device of claim 17, wherein the non-volatile memory is part of a storage module having a storage controller, and wherein the storage controller determines whether the monitored rate is below or above the first predetermined threshold.

25. The computing device of claim 17, wherein the processor is further configured to copy the first data from the SLC memory in the second swap area into the MLC memory in the first swap area.

26. The computing device of claim 25, wherein the computing device initiates and controls the copying.

27. The computing device of claim 25, wherein the non-volatile memory is part of a storage module, which has a storage controller, and wherein the storage controller controls the copying in response to a copy command from the computing device.

28. The computing device of claim 25, wherein the non-volatile memory is part of a memory die, and wherein the copying is performed as an on-chip copy process on the memory die.

29. The computing device of claim 17, wherein the computing device is a mobile device.

30. The computing device of claim 17, wherein the non-volatile memory is part of a storage module, and wherein the storage module is embedded in the computing device.

31. The computing device of claim 17, wherein the non-volatile memory is part of a storage module, and wherein the storage module is removably connected to the computing device.

32. The computing device of claim 17, wherein the non-volatile memory has a three-dimensional configuration.

33. A computing device comprising:

a volatile memory;

a non-volatile memory, wherein the non-volatile memory has multi-level cell (MLC) memory forming a first swap area and single-level cell (SLC) memory forming a second swap area;

means for monitoring a rate at which incoming data is being sent to the volatile memory;

means for, when the monitored rate is below a first predetermined threshold, swapping first data from the volatile memory to the first swap area of the non-volatile memory; and

means for, when the monitored rate is above the first predetermined threshold;

swapping the first data from the volatile memory to the second swap area of the non-volatile memory; and

when the monitored rate is below the first predetermined threshold, moving the first data from the second swap area of the non-volatile memory to the first swap area of the non-volatile memory.