System and method for deadlock-free pipelining

• US 9,928,639 B2
• Filed: 11/27/2013
• Issued: 03/27/2018
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Toksvig, Michael, Lindholm, Erik
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US14/092,816
• Publication Number:
  US 20140092114A1
• Time in Patent Office: 1,581 Days
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Claims

1. A processor group of a graphics processing unit, said processor group comprising:

a register file for storing data related to a plurality of threads concurrently operable within said processor group;

a texture unit for processing texture operations of said plurality of threads wherein each texture operation comprises a texture request operation and a corresponding texture read-back operation;

a buffer separate from said register file and within said texture unit for receiving results of said texture operations from said texture unit and storing said results, wherein said corresponding texture read-back operation reads from said buffer; and

a circuit for preventing deadlock within said texture unit and comprising a circuit for determining a number of texture request operations for said texture unit of a thread,

wherein said number of texture request operations comprises a number of multiple texture request operations that are present within said thread before a texture read-back operation is present within said thread.

2. A processor group as described in claim 1 further comprising a math functional unit for processing math operations of said plurality of threads, wherein said math functional unit is coupled to receive source operands from said register file and also coupled to store results into said register file.

3. A processor group as described in claim 1 further comprising a counter for maintaining a count of vacant memory resources of said buffer and said texture unit.

4. A processor group as described in claim 3 wherein said circuit for preventing deadlock further comprises:

a circuit for issuing said number of texture request operations to said texture unit provided there is sufficient vacant memory resources of said buffer and said texture unit to accommodate all of said number of texture request operations, otherwise not issuing any of said number of texture request operations to said texture unit.

5. A processor group as described in claim 1 wherein said circuit for preventing deadlock within said texture unit is further for preventing deadlock by allowing only a predetermined number of threads, or less, to concurrently operate with said texture unit wherein said predetermined number of threads is based on a number of texture request operations within each thread and based further on a size of said buffer and said texture unit.

6. A processor group as described in claim 5 wherein said predetermined number of threads is computed by dividing said size of said buffer and said size of said texture unit by said number of texture request operations within each thread.

7. A processor group of a graphics processing unit, said processor group comprising:

a register file for storing data related to a plurality of threads concurrently operable within said processor group;

a texture unit for processing texture operations of said plurality of threads wherein each texture operation comprises a texture request operation and a corresponding texture read-back operation; and

a buffer separate from said register file and within said texture unit for receiving results of said texture operations from said texture unit and storing said results, wherein said corresponding texture read-back operation reads from said buffer; and

a circuit for preventing deadlock within said texture unit, said circuit for preventing deadlock comprising;

a circuit for determining a number of texture request operations for said texture unit of a thread; and

a circuit for issuing said number of texture request operations to said texture unit provided there is sufficient vacant memory resources of said buffer and said texture unit to accommodate all of said number of texture request operations, otherwise not issuing any of said number of texture request operations to said texture unit,

wherein said number of texture request operations comprises a number of multiple texture request operations that are present within said thread before a texture read-back operation is present within said thread.

8. A processor group as described in claim 7 further comprising:

a math functional unit for processing math operations of said plurality of threads, wherein said math functional unit is coupled to receive source operands from said register file and also coupled to store results into said register file.

9. A processor group as described in claim 7 further comprising:

a counter operable for maintaining a count of vacant memory resources of said buffer and said texture unit.

10. A processor group as described in claim 9 wherein said maintaining of said count of vacant memory resources of said buffer comprises decreasing said count of said vacant memory resources of said buffer responsive to said issuing said number of texture operation requests to said texture unit.

11. A processor group as described in claim 9 wherein said maintaining of said count of vacant memory resources of said buffer comprises increasing said count of said vacant memory resources of said buffer responsive to said thread executing said read-back operations.

12. A processor group as described in claim 7 wherein said circuit for issuing said number of texture request operations to said texture unit is operable to issue only those grouped texture request operations that have allocated result space within said buffer wherein grouped texture request operations are all unissued sequential texture request operations within a thread that precede a first unissued texture read-back operation of said thread.

13. A processor group as described in claim 7 wherein said register file does not receive results from execution of said texture unit.

14. A circuit comprising:

a processor;

a register file;

a texture unit; and

a buffer separate from said register file and within said texture unit,

wherein said processor is configured to;

store data in said register file, wherein said data is related to a plurality of threads concurrently operable within said processor;

process texture operations of said plurality of threads using said texture unit, wherein each texture operation comprises a texture request operation and a corresponding texture read-back operation;

store results of said texture operations in said buffer, wherein said corresponding texture read-back operation reads from said buffer; and

prevent deadlock within said texture unit by allowing only a predetermined number of threads, or less, to concurrently operate with said texture unit wherein said predetermined number of threads is based on a number of texture request operations within each thread and based further on a size of said buffer and said texture unit, and

wherein said predetermined number of threads is computed by dividing said size of said buffer and said size of said texture unit by said number of texture request operations within each thread.

15. A circuit as described in claim 14, wherein said processor is configured to

process math operations of said plurality of threads, receive source operands from said register file, and store results into said register file.

16. A circuit as described in claim 14

wherein said processor is configured to maintain a count of vacant memory resources of said buffer and said texture unit.

17. A circuit as described in claim 16 wherein said processor is configured to maintain said count of vacant memory resources of said buffer by decreasing said count of said vacant memory resources of said buffer responsive to said issuing said number of texture operation requests to said texture unit.

18. A circuit as described in claim 17 wherein said processor is configured to maintain said count of vacant memory resources of said buffer further by increasing said count of said vacant memory resources of said buffer responsive to said thread executing said read-back operations.