Distributed pulse width modulation control
First Claim
Patent Images
1. A distributed pulse-width modulation system, comprising:
- an array of pulse-width modulation elements, each element comprising;
a digital memory for storing a multi-bit digital value, anda drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory; and
a system controller comprising;
a memory for storing a multi-bit digital value for each element, anda communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element,wherein the system controller comprises a timing circuit for providing timing signals to each element, wherein the timing signals control the rate at which the output device is driven in response to the multi-bit digital value stored in the digital memory,wherein the system controller comprises a memory for storing a full-bit digital value for each element, wherein the full-bit digital value comprises a plurality of multi-bit digital values, and the communication circuit communicates each multi-bit digital value of the full-bit digital value to each corresponding element sequentially,wherein the timing circuit, in response to the system controller, provides a timing signal with a first period for a first multi-bit digital value and provides a timing signal with a second period different from the first period for a second multi-bit digital value, andwherein the first multi-bit digital value represents the lower bits of the full-bit digital value and the second multi-bit digital value represents the upper bits of the full-bit digital value and the first and second periods are related by the relative value of the lower bits and the upper bits in the full-bit digital value.
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Abstract
A distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a multi-bit digital value and a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing a multi-bit digital value for each element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element.
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Citations
15 Claims
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1. A distributed pulse-width modulation system, comprising:
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an array of pulse-width modulation elements, each element comprising; a digital memory for storing a multi-bit digital value, and a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory; and a system controller comprising; a memory for storing a multi-bit digital value for each element, and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element, wherein the system controller comprises a timing circuit for providing timing signals to each element, wherein the timing signals control the rate at which the output device is driven in response to the multi-bit digital value stored in the digital memory, wherein the system controller comprises a memory for storing a full-bit digital value for each element, wherein the full-bit digital value comprises a plurality of multi-bit digital values, and the communication circuit communicates each multi-bit digital value of the full-bit digital value to each corresponding element sequentially, wherein the timing circuit, in response to the system controller, provides a timing signal with a first period for a first multi-bit digital value and provides a timing signal with a second period different from the first period for a second multi-bit digital value, and wherein the first multi-bit digital value represents the lower bits of the full-bit digital value and the second multi-bit digital value represents the upper bits of the full-bit digital value and the first and second periods are related by the relative value of the lower bits and the upper bits in the full-bit digital value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A distributed pulse-width modulation system, comprising:
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an array of pulse-width modulation elements, each element comprising; a digital memory for storing a multi-bit digital value, a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory, a first counter and a second counter, and a control circuit that alternates signals from the first counter and the second counter, wherein the output device is responsive to the alternating signals; a system controller comprising; a memory for storing a multi-bit digital value for each element, and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element; and a timing circuit for providing timing signals to each element, wherein the timing signals control the rate at which the output device is driven in response to the multi-bit digital value stored in the digital memory, wherein the first and second counters in each element are responsive to the timing signal.
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Specification