Semiconductor memory device

• US 9,928,916 B2
• Filed: 10/23/2017
• Issued: 03/27/2018
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Tokiwa, Naoya
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/790,494
• Publication Number:
  US 20180047451A1
• Time in Patent Office: 155 Days
• Field of Search: 36518511, 36518902
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Claims

1. A semiconductor memory device, comprising:

a memory block including a plurality of memory strings arranged in a first direction and a second direction, each memory string including a selection transistor and a plurality of memory cells arranged in a third direction, the first to third directions intersecting one another;

a plurality of bit lines arranged in the first direction and connected to the respective memory strings;

a plurality of select gate lines arranged in the second direction and connected to gates of the respective selection transistors of the memory strings;

a plurality of word lines arranged in the third direction and connected to gates of the respective memory cells of the memory strings; and

a controller configured to

perform an erase operation in a unit of the memory block, and

perform a sequence of erase verify operations, the erase verify operations including a first erase verify operation performed on a first group of the memory strings arranged in the first direction and a second erase verify operation performed consecutively after the first erase verify operation, on a second group of the memory strings arranged in the first direction, while maintaining voltages applied to the word lines between the first and second erase verify operations.

2. The semiconductor memory device of claim 1, wherein

the memory strings are arranged in a matrix configuration.

3. The semiconductor memory device of claim 1, further comprising:

a plurality of sense amplifiers connected to the respective bit lines,

wherein the controller is configured to apply enable signals to the respective sense amplifiers at least twice between the first and second erase verify operations.

4. The semiconductor memory device of claim 1, wherein

the controller is configured to store results of the erase verify operations in a cumulative manner.

5. The semiconductor memory device of claim 1, wherein

the controller is configured to suspend the erase verify operations when the number of failures is greater than or equal to a given number.

6. The semiconductor memory device of claim 1, wherein

each of the erase verify operations includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the groups of the memory strings arranged in the first direction.

7. A semiconductor memory system, comprising:

a semiconductor memory device including;

a memory block including a plurality of memory strings arranged in a first direction and a second direction, each memory string including a selection transistor and a plurality of memory cells arranged in a third direction, the first to third directions intersecting one another;

a plurality of bit lines arranged in the first direction and connected to the respective memory strings;

a plurality of select gate lines arranged in the second direction and connected to gates of the respective selection transistors of the memory strings;

a plurality of word lines arranged in the third direction and connected to gates of the respective memory cells of the memory strings; and

a control circuit; and

a controller device configured to send an instruction to the control circuit of the storage device, the instruction causing the control circuit to

perform an erase operation in a unit of the memory block, and

perform a sequence of erase verify operations, the erase verify operations including a first erase verify operation performed on a first group of the memory strings arranged in the first direction and a second erase verify operation performed consecutively after the first erase verify operation, on a second group of the memory strings arranged in the first direction, while maintaining voltages applied to the word lines between the first and second erase verify operations.

8. The semiconductor memory system of claim 7, wherein

the memory strings are arranged in a matrix configuration.

9. The semiconductor memory system of claim 7, further comprising:

a plurality of sense amplifiers connected to the respective bit lines,

wherein the controller is configured to apply enable signals to the respective sense amplifiers at least twice between the first and second erase verify operations.

10. The semiconductor memory system of claim 7, wherein

the controller is configured to store results of the erase verify operations in a cumulative manner.

11. The semiconductor memory system of claim 7, wherein

the controller is configured to suspend the erase verify operations when the number of failures is greater than or equal to a given number.

12. The semiconductor memory system of claim 7, wherein

each of the erase verify operations includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the groups of the memory strings arranged in the first direction.

13. A method for operating a semiconductor memory device,

the semiconductor memory device including:

a memory block including a plurality of memory strings arranged in a first direction and a second direction, each memory string including a selection transistor and a plurality of memory cells arranged in a third direction, the first to third directions intersecting one another;

a plurality of bit lines arranged in the first direction and connected to the respective memory strings;

a plurality of select gate lines arranged in the second direction and connected to gates of the respective selection transistors of the memory strings; and

a plurality of word lines arranged in the third direction and connected to gates of the respective memory cells of the memory strings;

the method comprising;

performing an erase operation in a unit of the memory block, and

performing a sequence of erase verify operations, the erase verify operations including a first erase verify operation performed on a first group of the memory strings arranged in the first direction and a second erase verify operation performed consecutively after the first erase verify operation, on a second group of the memory strings arranged in the first direction, while maintaining voltages applied to the word lines between the first and second erase verify operations.

14. The method of claim 13, wherein

the memory strings are arranged in matrix configuration.

15. The method of claim 13, wherein

a plurality of sense amplifiers are connected to the respective bit lines,

the method further comprises

applying enable signals to the respective sense amplifiers at least twice between the first and second erase verify operations.

16. The method of claim 13, further comprising:

storing results of the erase verify operations in a cumulative manner.

17. The method of claim 13, further comprising

suspending the erase verify operations when the number of failures is greater than or equal to a given number.

18. The method of claim 13, wherein

each of the erase verify operations includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the groups of the memory strings arranged in the first direction.