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Semiconductor memory device

  • US 9,928,916 B2
  • Filed: 10/23/2017
  • Issued: 03/27/2018
  • Est. Priority Date: 09/06/2012
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a memory block including a plurality of memory strings arranged in a first direction and a second direction, each memory string including a selection transistor and a plurality of memory cells arranged in a third direction, the first to third directions intersecting one another;

    a plurality of bit lines arranged in the first direction and connected to the respective memory strings;

    a plurality of select gate lines arranged in the second direction and connected to gates of the respective selection transistors of the memory strings;

    a plurality of word lines arranged in the third direction and connected to gates of the respective memory cells of the memory strings; and

    a controller configured toperform an erase operation in a unit of the memory block, andperform a sequence of erase verify operations, the erase verify operations including a first erase verify operation performed on a first group of the memory strings arranged in the first direction and a second erase verify operation performed consecutively after the first erase verify operation, on a second group of the memory strings arranged in the first direction, while maintaining voltages applied to the word lines between the first and second erase verify operations.

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