Insulating structure, a method of forming an insulating structure, and a chip scale isolator including such an insulating structure

• US 9,929,038 B2
• Filed: 03/07/2013
• Issued: 03/27/2018
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: O'Sullivan, Laurence Brendan
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/788,410
• Publication Number:
  US 20140252533A1
• Time in Patent Office: 1,846 Days
• Field of Search: 257506, 257632, 257 48, 257531, 257666, 307 91, 307104, 361813, 361767, 361783, 455 78, 4555501, 336200, 336192, 336 1, 336223, 29606, 296021, 324415
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region.

Claims

1. A method of forming an insulating structure, comprising

forming an electrical contact region to a first transmitting or receiving element of an isolator;

forming an electrical contact region to a second transmitting or receiving element of the isolator spatially separated from the first transmitting or receiving element of the isolator;

forming an insulating layer extending at least part of a distance between the electrical contact region to the first transmitting or receiving element of the isolator and the electrical contact region to the second transmitting or receiving element of the isolator, the insulating layer having a nonplanar surface including at least first and second trenches between the electrical contact region to the first transmitting or receiving element of the isolator and the electrical contact region to the second transmitting or receiving element of the isolator, wherein a bottom boundary and side walls of each of the first and second trenches are formed of a same insulating material.

2. The method as claimed in claim 1, wherein the insulating layer is a first insulating layer, and wherein the method further comprises forming the first transmitting or receiving element of the isolator between the first insulating layer and a second insulating layer.

3. The method as claimed in claim 1, wherein forming the insulating layer comprises forming the insulating layer to cover sides of an underlying insulating layer.

4. The method as claimed in claim 1, wherein the first transmitting or receiving element and the second transmitting or receiving element form a transformer.

5. The method as claimed in claim 1, wherein forming the insulating layer comprises forming the insulating layer as an uppermost layer of the isolator.

6. The method as claimed in claim 1, further comprising forming the electrical contact region to the first transmitting or receiving element of the isolator as a high voltage contact region and the electrical contact region to the second transmitting or receiving element of the isolator as a low voltage contact region.

7. The method as claimed in claim 4, further comprising:

forming the second transmitting or receiving element on a substrate, and depositing M layers of insulator over a portion of the substrate containing the second transmitting or receiving element.

8. The method as claimed in claim 6, in which the second transmitting or receiving element forms part of a transformer.

9. The method as claimed in claim 1, further comprising packaging the insulating structure within an integrated circuit package such that the first and second trenches are filled with a packaging mould compound within the integrated circuit package.

10. The method as claimed in claim 1, in which the insulating layer comprises polyimide or oxide.

11. The method as claimed in claim 1, further comprising forming a third trench within the insulating layer, wherein the first and third trenches are respectively adjacent to first and second sides of the electrical contact region to the first transmitting or receiving element.

12. The method as claimed in claim 1, wherein the at least first and second trenches are bounded by a plurality of walls.

13. The method as claimed in claim 9, wherein the packaging mould compound engages with the nonplanar surface of the insulating layer.

14. The method as claimed in claim 13, wherein the packaging mould compound encapsulates the isolator.

15. The method as claimed in claim 1, wherein forming the insulating layer comprises selectively etching the first and second trenches with a plasma etching process.

16. The method as claimed in claim 1, wherein forming the electrical contact region to the first transmitting or receiving element comprises forming the electrical contact region to the first transmitting or receiving element at a first lateral position and first vertical position of the isolator, wherein forming the electrical contact region to the second transmitting or receiving element comprises forming the electrical contact region to the second transmitting or receiving element at a second lateral position and a second vertical position of the isolator, and wherein the first and second trenches are formed at lateral positions between the first and second lateral positions and at a third vertical position such that the second vertical position is between the first and third vertical positions.

17. The method as claimed in claim 16, further comprising encapsulating the isolator in a packaging compound.

18. The method as claimed in claim 1, further comprising forming the first trench as a continuous trench in a plane of the insulating layer.

19. The method as claimed in claim 1, further comprising forming the first trench as a discontinuous trench in a plane of the insulting layer.

20. The method as claimed in claim 1, further comprising forming the first and second trenches as concentric trenches in a plane of the insulating layer.