Leadless electronic packages for GAN devices

• US 9,929,079 B2
• Filed: 03/21/2017
• Issued: 03/27/2018
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Navitas Semiconductor, Inc.
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/465,433
• Publication Number:
  US 20170194237A1
• Time in Patent Office: 371 Days
• Field of Search: 257 76
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05014 being square
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/4814 the wire connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85186 : connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49589 : Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/04 : the devices not having separate containers
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1426 : Driver
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H02M 3/158 : including plural semiconductor devices as final control devices for a single load

Abstract

Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.

Claims

1. An electronic component comprising:

a first lead, a second lead, and a third lead;

at least a first semiconductor device having a device top surface opposite a device bottom surface, wherein the device bottom surface is attached to a top surface of the first lead and the device top surface includes at least one source terminal that is electrically coupled to the first lead, at least one drain terminal that is electrically coupled to the second lead and at least one input terminal that is electrically coupled to the third lead; and

an electrically insulative encapsulant formed around the at least a first semiconductor device and around at least a portion of the first lead, the second lead and the third lead.

2. The electronic component of claim 1 further comprising a second semiconductor device attached to the second lead.

3. The electronic component of claim 2 wherein the at least a first semiconductor device and the second semiconductor device are GaN-based devices.

4. The electronic component of claim 3 wherein the at least a first semiconductor device and the second semiconductor device each include a layer of GaN on a layer of silicon and are able to withstand voltages in the range of 650 Volts with a specific resistance between 1 and 10 milliohm-cm².

5. The electronic component of claim 2 wherein the second semiconductor device includes a high side transistor monolithically integrated with a high side drive circuit.

6. The electronic component of claim 2 wherein the second semiconductor device includes a second source terminal electrically coupled to the second lead and a second drain terminal coupled to a fourth lead.

7. The electronic component of claim 6 wherein the electronic component functions as a half-bridge power conversion component and the first lead is a ground connection, the second lead is a switch-node connection and the fourth lead is an input voltage connection.

8. The electronic component of claim 6 wherein the first lead, the second lead and the fourth lead are arranged in an “

L”

shape with the first lead forming a first leg of the “

L”

shape, the second lead forming a corner of the “

L”

shape and the fourth lead forming a second leg of the “

L”

shape.

9. The electronic component of claim 6 wherein the first lead, the second lead and the fourth lead are arranged in a linear shape with the first lead forming a first portion of the linear shape, the second lead forming a central portion of the linear shape and the fourth lead forming a last portion of the linear shape.

10. The electronic component of claim 6 wherein the second lead is separated from the fourth lead by a distance of 0.8 to 3.0 millimeters.

11. The electronic component of claim 2 wherein the second semiconductor device includes a transistor having a source electrically coupled to the at least one drain terminal and a drain coupled to the second lead.

12. The electronic component of claim 2 wherein the second semiconductor device is attached to a dielectric substrate that is attached to the top surface of the first lead.

13. The electronic component of claim 12 further comprising a passive electronic component electrically coupled to the dielectric substrate.

14. The electronic component of claim 1 wherein the first lead is separated from the second lead by a distance of 0.8 to 3.0 millimeters.

15. The electronic component of claim 1 wherein the third lead is a PWM input.

16. The electronic component of claim 1 wherein the at least a first semiconductor device includes a low side transistor monolithically integrated with a low side drive circuit.

17. The electronic component of claim 1 wherein the at least a first semiconductor device includes a transistor having a source coupled to the at least one source terminal, a drain coupled to at least one drain terminal and a gate coupled to the at least one input terminal.

18. The electronic component of claim 1 wherein the device top surface of the at least a first semiconductor device includes a level shift output terminal that is configured to be electrically coupled to a level shift input on a second semiconductor device.

19. The electronic component of claim 1 wherein the at least a first semiconductor device includes a bidirectional transistor.

20. The electronic component of claim 19 wherein the bidirectional transistor includes a second drain terminal coupled to a fourth lead.

21. The electronic component of claim 20 wherein the second lead is separated from the fourth lead by a distance of 1.1 to 3.0 millimeters, and the second and fourth leads are separated from the first lead by a distance of 1.1 to 3.0 millimeters.

22. The electronic component of claim 19 wherein the bidirectional transistor includes a PWM input terminal coupled to a fifth lead.

27. The electronic component of claim 1 wherein the first GaN-based die includes a low side transistor monolithically integrated with a low side drive circuit.

28. The electronic component of claim 1 wherein the first GaN-based die includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.

23. An electronic component comprising:

an electrically conductive package base including a first lead, a second lead, and a third lead;

a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and

an encapsulant formed over the first GaN-based die and at least a top surface of the electrically conductive package base.

24. The electronic component of claim 23 further comprising a second GaN-based die attached to the second lead.

25. The electronic component of claim 24 wherein the second GaN-based die includes a second source terminal electrically coupled to the second lead and a second drain terminal coupled to a fourth lead.

26. The electronic component of claim 25 wherein the first lead, the second lead and the fourth lead are arranged in an “

L”

shape with the first lead forming a first leg of the “

L”

shape, the second lead forming a corner of the “

L”

shape and the fourth lead forming a second leg of the “

L”

shape.

29. A packaged electronic device comprising:

a package including a leadframe having a first lead, a second lead, and a third lead;

at least a first integrated circuit (IC) die having a top surface opposite a bottom surface, wherein the bottom surface is positioned on the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and

an electrically insulative encapsulant formed around the at least a first IC and around at least a portion of the leadframe.

30. The packaged electronic device of claim 29 further comprising a second integrated circuit attached to the second lead.

31. The packaged electronic device of claim 30 wherein the at least a first integrated circuit and the second integrated circuit are GaN-based devices.

32. The packaged electronic device of claim 30 wherein the second integrated circuit includes a second source terminal electrically coupled to the second lead and a second drain terminal coupled to a fourth lead.

33. The packaged electronic device of claim 32 wherein the first lead, the second lead and the fourth lead are arranged in an “

L”

shape with the first lead forming a first leg of the “

L”

shape, the second lead forming a corner of the “

L”

shape and the fourth lead forming a second leg of the “

L”

shape.

34. The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a low side transistor monolithically integrated with a low side drive circuit.

35. The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.