Device with interconnection structure for forming a conduction path or a conducting plane with high decoupling capacitance

• US 9,929,084 B2
• Filed: 02/09/2017
• Issued: 03/27/2018
• Est. Priority Date: 02/11/2016
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Gonzalez Jimenez, Jose-Luis
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US15/428,502
• Publication Number:
  US 20170236778A1
• Time in Patent Office: 411 Days
• Field of Search: 257774
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00

Abstract

Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which:

• • all the lines of a same array extend in a same plane and form an equipotential;
  • a first pattern of a first array is such that the lines of the first array intersect at several intersections;
  • a third pattern of a third array is similar, superimposed and aligned with the first pattern;
  • a second pattern of a second array arranged between the first and third arrays is such that the lines of the second array intersect at several intersections offset with respect to those of the first and third patterns;
  • a first conducting via extends from a line of the first and/or third array and is not in contact with the second array.

Claims

1. Electronic device comprising an electrical interconnection structure forming at least one electrical conduction path between at least two points of the electronic device and/or at least one electrically conducting plane, and comprising an alternating stack of arrays of conducting lines and dielectric layers in which:

all the conducting lines of a same array extend in a same plane and form an equipotential;

a first pattern of the conducting lines of a first array is such that at least one first of the conducting lines of the first array extends along at least one first direction and several second of the conducting lines of the first array intersect the first of the conducting lines of the first array at several intersections;

a third pattern of the conducting lines of a third array is similar to the first pattern, the first and third patterns being superimposed one on top of the other and such that the intersections of the first pattern are aligned with intersections of the third pattern along an axis substantially perpendicular to the planes in which the conducting lines of the first and third arrays extend;

a second pattern of conducting lines of a second array arranged between the first and third arrays of conducting lines is such that at least one first of the conducting lines of the second array extends along the first direction and several second of the conducting lines of the second array intersect the first of the conducting lines of the second array at several intersections offset with respect to the intersections of the first and third patterns;

at least one first conducting via extends through at least one part of at least one of the dielectric layers interposed between the first and third arrays of conducting lines, is in contact with at least one of the conducting lines of the first array and/or of the third array and is such that a section of the first conducting via projected in a plane in which the conducting lines of the second array pass is not in contact with the conducting lines of the second array.

2. Electronic device according to claim 1, comprising several first conducting vias extending through the dielectric layers interposed between the first and third arrays of conducting lines and each electrically connecting one of the intersections of the first array of conducting lines to one of the intersections of the third array of conducting lines through a conducting portion of the second array which is electrically insulated from the conducting lines of the second array.

3. Electronic device according to claim 1, further comprising at least one second conducting via extending through at least one part of at least one of the dielectric layers interposed between the first and third arrays of conducting lines, in contact with at least one of the conducting lines of the second array and such that a section of the at least one second conducting via projected in a plane in which the conducting lines of the first array pass is not in contact with the conducting lines of the first array.

4. Electronic device according to claim 3, comprising several second conducting vias extending through the dielectric layers interposed between the first and third arrays of conducting lines, each being in contact with one of the intersections of the second array of conducting lines and with a conducting portion of the first array which is electrically insulated from the conducting lines of the first array and/or a conducting portion of the third array which is electrically insulated from the conducting lines of the third array.

5. Electronic device according to claim 1, in which the first and third patterns of the conducting lines of the first and third arrays correspond respectively to a first and a third grid layouts aligned and superimposed one on top of the other, and in which the second pattern of the conducting lines of the second array corresponds to a second grid layout offset with respect to the first and third grid layouts.

6. Electronic device according to claim 2, further comprising several second conducting vias extending through the dielectric layers interposed between the first and third arrays of conducting lines, each being in contact with one of the intersections of the second array of conducting lines and with a conducting portion of the first array which is electrically insulated from the conducting lines of the first array and/or a conducting portion of the third array which is electrically insulated from the conducting lines of the third array, and such that a section of each second conducting via projected in a plane in which the conducting lines of the first array pass is not in contact with the conducting lines of the first array,

in which the first and third patterns of the conducting lines of the first and third arrays correspond respectively to a first and a third grid layouts aligned and superimposed one on top of the other, and in which the second pattern of the conducting lines of the second array corresponds to a second grid layout offset with respect to the first and third grid layouts,

and in which the first conducting vias traverse openings formed in the second grid layout and the second conducting vias traverse openings formed in at least one of the first and third grid layouts.

7. Electronic device according to claim 1, in which the conducting lines of a same array intersect in a substantially perpendicular manner.

8. Electronic device according to claim 1, in which at least one of the first of the conducting lines of one of the arrays is interrupted.

9. Electronic device according to claim 1, further comprising one or more other arrays of conducting lines superimposed on the first, second and third arrays of conducting lines and of which the conducting lines form a similar pattern and aligned with the first or with the second pattern such that the patterns formed by the conducting lines of the one or more other arrays correspond to an alternating superposition of the first and second patterns.

10. Electronic device according to claim 1, further comprising at least one analogue integrated circuit and in which the interconnection structure forms ground and electrical supply planes of said at least one analogue integrated circuit.

11. Method for producing an electronic device comprising an electrical interconnection structure forming at least one electrical conduction path between at least two points of the electronic device and/or at least one electrically conducting plane, in which the method comprises a step of computer aided design of the electrical conduction path and/or of the electrically conducting plane from several similar connection cells each modelling a part of an alternating stack of arrays of conducting lines and dielectric layers in which:

all the conducting lines of a same array extend in a same plane and form an equipotential;

a first pattern of the conducting lines of a first array is such that at least one first of the conducting lines of the first array extends along at least one first direction and several second of the conducting lines of the first array intersect the first of the conducting lines of the first array at several intersections;

a third pattern of the conducting lines of a third array is similar to the first pattern, the first and third patterns being superimposed one on top of the other and such that the intersections of the first pattern are aligned with intersections of the third pattern along an axis substantially perpendicular to the planes in which the conducting lines of the first and third arrays extend;

a second pattern of the conducting lines of a second array arranged between the first and third arrays of conducting lines is such that at least one first of the conducting lines of the second array extends along the first direction and several second of the conducting lines of the second array intersect the first of the conducting lines of the second array at several intersections offset with respect to the intersections of the first and third patterns;

at least one first conducting via extends through at least one part of at least one of the dielectric layers interposed between the first and third arrays of conducting lines, is in contact with at least one of the conducting lines of the first array and/or of the third array and such that a section of the first conducting via projected in a plane in which the conducting lines of the second array pass is not in contact with the conducting lines of the second array;

and in which, during the step of computer aided design of the electrical conduction path and/or of the electrically conducting plane, a plurality of connection cells are juxtaposed and placed in contact laterally with each other to form the electrical conduction path and/or the electrically conducting plane.

12. Method according to claim 11, in which the first and third patterns of the conducting lines of the first and third arrays correspond to a first and a third grid layouts aligned one on top of the other, and in which the second pattern of the conducting lines of the second array corresponds to a second grid layout offset with respect to the first and third grid layouts.

13. Method according to claim 11, in which each of the connection cells is such that at least one of the conducting lines of each of the arrays extends between a first corner or a first edge of the connection cell and a second corner or a second edge of the connection cell.

14. Method according to claim 11, in which each of the connection cells comprises at least one part of the first of the conducting lines and at least one of the second of the conducting lines of each of the arrays.