Semiconductor device including optimized gate stack profile

• US 9,929,250 B1
• Filed: 09/27/2016
• Issued: 03/27/2018
• Est. Priority Date: 09/27/2016
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Victor, Han, Jin Ping
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US15/277,722
• Publication Number:
  US 20180090596A1
• Time in Patent Office: 546 Days
• Field of Search: 257409
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.

Claims

1. A method of fabricating a semiconductor device including an enhanced electrically conductive gate profile, the method comprising:

forming a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height;

forming a sacrificial gate atop the semiconductor substrate, the sacrificial gate including a base portion formed on an upper surface of the semiconductor substrate and an upper surface portion located opposite the base portion;

expanding the upper surface portion of the sacrificial gate with respect to the base portion to form an expanded sacrificial gate;

removing the expanded sacrificial gate to form a gate trench including a base region having a first trench length and an upper surface region having a second trench length greater than the first trench length; and

filling the gate trench with an electrically conductive material so as to form an electrically conductive gate having the enhanced electrically conductive gate profile,

wherein the electrically conductive gate extends along the second axis between a base and an upper portion to define a gate height, and wherein the enhanced electrically conductive gate profile includes the upper portion extending further along the first axis than the base to define a non-uniform shape of the electrically conductive gate.

2. The method of claim 1, wherein forming the sacrificial gate comprises:

forming a graded sacrificial layer including a dominant thermal sensitive material atop the semiconductor substrate, a concentration of the dominant thermal sensitive material being greater at an upper surface portion of the graded sacrificial layer than at the base portion of the graded sacrificial layer; and

patterning the graded sacrificial material to form the sacrificial gate, wherein the concentration of the dominant thermal sensitive material is greater at the upper surface portion of the sacrificial gate than at the base portion of the sacrificial gate.

3. The method of claim 2, wherein the sacrificial layer comprises silicon germanium (SiGe), and wherein the dominant thermal sensitive material is Ge.

4. The method of claim 2, wherein the sacrificial layer comprises silicon carbide (SiC), and wherein the dominant thermal sensitive material is Si.

5. The method of claim 1, wherein forming the sacrificial gate comprises:

forming, atop the semiconductor substrate, a sacrificial stack including a plurality of individual sacrificial layers stacked along the second axis, the plurality of individual sacrificial layers including a first sacrificial layer having a first concentration of a first thermal sensitive material and a second sacrificial layer formed atop the first sacrificial layer and having a second concentration of a second thermal sensitive semiconductor substrate that is greater than the first concentration;

patterning the graded sacrificial material to form a multi-layer sacrificial gate such that the first thermal sensitive material is located at the upper surface portion of the multi-layer sacrificial gate, and the second thermal sensitive material is interposed between the first thermal sensitive material and the upper surface of the semiconductor substrate.

6. The method of claim 5, wherein forming the sacrificial stack comprises:

forming a base sacrificial layer on an upper surface of the semiconductor substrate;

forming the second thermal sensitive material on an upper surface of the base sacrificial layer; and

forming the first thermal sensitive material on an upper surface of the second sacrificial layer.

7. The method of claim 6, wherein the base sacrificial layer comprises poly-silicon.

8. A method of enhancing a gate profile of an electrically conductive gate included in a field effect transistor (FET), the method comprising:

forming a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height;

forming a sacrificial gate atop the semiconductor substrate, the sacrificial gate having a thermal expansion coefficient that varies along the second axis between a base portion disposed on the semiconductor substrate and an upper surface portion of the sacrificial gate located opposite the base portion;

annealing the sacrificial gate such that the upper surface portion expands along the first axis further than the base portion; and

replacing the sacrificial gate with an electrically conductive gate including a base that extends along the first axis to define a first gate length and an upper surface that extends along the first axis to define as second gate length that is greater than the first gate length.

9. The method of claim 8, wherein replacing the sacrificial gate includes:

removing the sacrificial gate after performing the annealing to form a gate trench including a base region having a first trench length and an upper surface region having a second trench length greater than the first trench length; and

filling the gate trench with an electrically conductive material so as to form the electrically conductive gate.

10. The method of claim 9, wherein sidewalls of the electrically conductive gate extend along the second axis between a base and an upper gate surface to define a gate height, and wherein the enhanced electrically conductive gate profile includes the upper portion extending further along the first axis than the base.

11. The method of claim 10, wherein forming the sacrificial gate comprises:

forming a graded sacrificial layer including a dominant thermal sensitive material atop the semiconductor substrate, a concentration of the dominant thermal sensitive material being greater at an upper surface portion of the graded sacrificial layer than at the base portion of the graded sacrificial layer; and

patterning the graded sacrificial material to form the sacrificial gate, wherein the concentration of the dominant thermal sensitive material is greater at the upper surface portion of the sacrificial gate than at the base portion of the sacrificial gate.

12. The method of claim 11, wherein the sacrificial layer comprises silicon germanium (SiGe), and wherein the dominant thermal sensitive material is Ge.

13. The method of claim 11, wherein the sacrificial layer comprises silicon carbide (SiC), and wherein the dominant thermal sensitive material is Si.

14. The method of claim 10, wherein forming the sacrificial gate comprises:

forming, atop the semiconductor substrate, a sacrificial stack including a plurality of individual sacrificial layers stacked along the second axis, the plurality of individual sacrificial layers including a first sacrificial layer having a first concentration of a first thermal sensitive material and a second sacrificial layer formed atop the first sacrificial layer and having a second concentration of a second thermal sensitive semiconductor substrate that is greater than the first concentration;

patterning the graded sacrificial material to form a multi-layer sacrificial gate such that the first thermal sensitive material is located at the upper surface portion of the multi-layer sacrificial gate, and the second thermal sensitive material is interposed between the first thermal sensitive material and the upper surface of the semiconductor substrate.

15. The method of claim 14, wherein forming the sacrificial stack comprises:

forming a base sacrificial layer on an upper surface of the semiconductor substrate;

forming the second thermal sensitive material on an upper surface of the base sacrificial layer; and

forming the first thermal sensitive material on an upper surface of the second sacrificial layer.

16. The method of claim 15, wherein the base sacrificial layer comprises poly-silicon.

17. A semiconductor device including an electrically conductive gate having an enhanced gate profile, the semiconductor device comprising:

a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height, the semiconductor substrate including a channel region interposed between opposing source/drain regions;

a gate stack atop the semiconductor substrate, the gate stack including an electrically conductive gate atop the channel region, the electrically conductive gate including sidewalls extending between a base and an upper surface to define a gate height,

wherein a gate length of the electrically conductive gate continuously increases non-uniformly as the gate height increases from the base to the upper surface.

18. The semiconductor device of claim 17, wherein the gate stack comprises:

a gate dielectric layer on an upper surface of the semiconductor substrate; and

a work function metal layer on an upper surface of the gate dielectric layer and the sidewalls of the electrically conductive gate,

wherein the base of the electrically conductive gate is directly on the work function metal layer.

19. The semiconductor device of claim 18, wherein the electrically conductive gate completely comprises a metal material.