Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

• US 9,929,257 B2
• Filed: 01/12/2017
• Issued: 03/27/2018
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Diaz, Carlos H, Yeo, Yee-Chia
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/404,712
• Publication Number:
  US 20170125554A1
• Time in Patent Office: 439 Days
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1207 : combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/127 : with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 : characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 : in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Claims

1. A method comprising:

forming a first source/drain contact region;

forming a first gate electrode over the first source/drain contact region and over a substrate;

forming a first opening through the first gate electrode to the first source/drain contact region;

forming a first gate dielectric along a first sidewall of the first opening;

depositing a first bismuth-containing semiconductor material in the first opening to form a first bismuth-containing channel structure, the first gate dielectric being disposed between the first gate electrode and the first bismuth-containing channel structure, the first bismuth-containing channel structure being connected to the first source/drain contact region;

forming a second source/drain contact region over and connected to the first bismuth-containing channel structure; and

crystallizing the first bismuth-containing semiconductor material, the crystallizing comprising performing an anneal.

2. The method of claim 1, wherein the depositing the first bismuth-containing semiconductor material comprises doping the first bismuth-containing semiconductor material with a p-type dopant or an n-type dopant during the depositing the first bismuth-containing semiconductor material.

3. The method of claim 1, wherein the anneal has a temperature greater than 271.4°

C. and less than or equal to 400°

C.

4. The method of claim 1 further comprising:

forming a third source/drain contact region over the second source/drain contact region;

forming a second gate electrode over the third source/drain contact region;

forming a second opening through the second gate electrode to the third source/drain contact region;

forming a second gate dielectric along a second sidewall of the second opening;

depositing a second bismuth-containing material in the second opening to form a second bismuth-containing channel structure, the second gate dielectric being disposed between the second gate electrode and the second bismuth-containing channel structure, the second bismuth-containing channel structure being connected to the third source/drain contact region; and

forming a fourth source/drain contact region over and connected to the second bismuth-containing channel structure,

wherein the crystallizing the first bismuth-containing semiconductor material further crystallizes the second bismuth-containing material, the anneal being performed after the forming the fourth source/drain contact region.

5. The method of claim 4 further comprising forming an interconnect structure between the second source/drain contact region and the third source/drain contact region.

6. A method comprising:

forming a first source/drain contact over a substrate;

forming a dielectric layer over the first source/drain contact;

forming an opening in the dielectric layer to the first source/drain contact, the opening having a sidewall extending above the first source/drain contact;

forming a gate dielectric along the sidewall of the opening;

depositing a bismuth-containing semiconductor material in the opening to form a bismuth-containing channel structure, the gate dielectric being disposed between the opening and the bismuth-containing channel structure;

forming a second source/drain contact connected to and over the bismuth-containing channel structure; and

crystallizing the bismuth-containing semiconductor material.

7. The method of claim 6, wherein the bismuth-containing semiconductor material is monocrystalline.

8. The method of claim 6, wherein the bismuth-containing semiconductor material comprises a dopant.

9. The method of claim 6, wherein the crystallizing comprises performing an anneal.

10. A method comprising:

forming a first transistor, the first transistor comprising a first bismuth-containing channel structure, the first bismuth-containing channel structure comprising a first doping profile;

forming a second transistor, the second transistor comprising a second bismuth-containing channel structure, the second bismuth-containing channel structure comprising a second doping profile, the second doping profile complementary to the first doping profile;

forming a first interconnect structure over the second bismuth-containing channel structure; and

crystallizing the first bismuth-containing channel structure and the second bismuth-containing channel structure.

11. The method of claim 10, wherein the crystallizing is performed using a thermal anneal.

12. The method of claim 11, wherein the thermal anneal comprises a temperature greater than 271.4°

C. and less than or equal to 400°

C.

13. The method of claim 10, further comprising, before forming the first transistor and the second transistor, forming a second interconnect structure over a substrate, wherein forming the first transistor and the second transistor comprises forming the first transistor and the second transistor over the second interconnect structure.

14. The method of claim 13, further comprising forming a first source/drain contact region over the second interconnect structure.

15. The method of claim 14, wherein the first bismuth-containing channel structure is connected to the first source/drain contact region.

16. The method of claim 15, further comprising forming a second source/drain contact region over and connected to the first bismuth-containing channel structure.

17. The method of claim 16, further comprising forming a second gate electrode, a third source/drain contact region over the second interconnect structure.

18. The method of claim 17, further comprising forming a fourth source/drain contact region above and electrically connected to the second bismuth-containing channel structure.

19. The method of claim 18, wherein the second bismuth-containing channel structure is connected to the third source/drain contact region.

20. The method of claim 19, wherein the fourth source/drain contact region contacts the second bismuth-containing channel structure.