Three-level active neutral point converter

• US 9,929,677 B2
• Filed: 07/08/2014
• Issued: 03/27/2018
• Est. Priority Date: 07/17/2013
• Status: Active Grant

• Current Assignee: Innomotics GmbH (Siemens AG)
• Original Assignee: Siemens AG
• Inventors: Eckel, Hans-Gnter
• Primary Examiner(s): Mehari, Yemane
• Application Number:
  US14/905,613
• Publication Number:
  US 20160181948A1
• Time in Patent Office: 1,358 Days
• Field of Search: 363 40, 363 41, 363 50, 363 55, 363 5601, 363 5602, 363 65, 363 98, 363131, 363132
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

The invention relates to a active-neutral point clamped converter having at least one half-bridge circuit connected into a DC voltage circuit. Each half-bridge circuit has a high-potential-side input half-bridge and a low-potential-side input half-bridge in series. The half-bridge circuit further has an output half-bridge connected between center taps of the input half-bridges. The total inductance within the output half-bridges and between the three half-bridges is dimensioned such that if any of the power semiconductors of the half-bridge circuit fails, a short-circuit can be reliably disconnected via a shorted circuit formed between the three half-bridges of the half-bridge circuit by the intact power semiconductors in said shorted circuit.

Claims

1. A three-level converter, comprising:

an input-side DC circuit having a high-potential rail and a low-potential rail;

at least one half-bridge circuit, the half-bridge circuit having a high-potential side input half-bridge, a low-potential side input half-bridge and an output half-bridge, wherein the two input half-bridges are connected in series between the high-potential rail and the low-potential rail of the input-side DC circuit, and the output half-bridge is connected between a center tap of the high-potential side input half-bridge and a center tap of the low-potential side input half-bridge, and

a phase terminal connected to a center tap of the output half-bridge, said phase terminal being adapted to be connected to a load circuit,

wherein the total of the inductance within the output half-bridge connected between the high-potential side input half-bridge and the low-potential side input half-bridge, and the inductance between the high-potential side input half-bridge and the output half-bridge, and the inductance between the low-potential side input half-bridge and the output half-bridge is designed to have a value such that, in the event of a failure of any one power semiconductor in the half-bridge circuit, a short-circuit via a short-circuit path formed between the three half-bridges of the half-bridge circuit can be reliably cut off by the intact power semiconductors in that short-circuit path,

wherein the value of said total inductance has an inductance value between 100 nH and 10 μ

H, and

wherein the three-level converter is designed for use in a Megawatt range of 1 MW-20 MW.

2. The three-level converter of claim 1, wherein a load circuit is connected to the phase terminal.

3. The three-level converter of claim 1, further comprising at least one choke arranged within the output half-bridge.

4. The three-level converter of claim 1, further comprising at least one choke arranged between the high-potential side input half-bridge and the low-potential side input half-bridge.

5. The three-level converter of claim 1, further comprising at least one choke arranged between the high-potential side input half-bridge and the output half-bridge.

6. The three-level converter of claim 1, further comprising at least one choke arranged between the low-potential side input half-bridge and the output half-bridge.

7. The three-level converter of claim 1, wherein the three half-bridges of the same half-bridge circuit are spaced apart in such a way as to rule out mechanical or thermal damage to, or impairment of, one half-bridge by one of the two other half-bridges.

8. The three-level converter of claim 1, wherein the three half-bridges of the same half-bridge circuit are mechanically separated from one another in such a way as to rule out mechanical or thermal damage to, or impairment of, one half-bridge by one of the two other half-bridges.

9. The three-level converter of claim 1, wherein the DC circuit is designed in such a way as to rule out an electrical flashover between the high-potential rail and the low-potential rail.

10. The three-level converter of claim 1, wherein the high-potential side input half-bridge and the low-potential side input half-bridge are each designed to have a low inductance.