Communications based adjustments of an offset capacitive voltage

• US 9,929,696 B2
• Filed: 01/24/2014
• Issued: 03/27/2018
• Est. Priority Date: 01/24/2013
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Kay, Michael R., Nag, Manbir Singh
• Primary Examiner(s): Tran, Pablo
• Application Number:
  US14/163,256
• Publication Number:
  US 20140203869A1
• Time in Patent Office: 1,523 Days
• Field of Search: 4551272, 4551273, 4551271, 4551274, 455102, 455108, 330127, 330 75
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/471 the voltage being sensed
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/24 of transmitter output stages

Abstract

A parallel amplifier and an offset capacitance voltage control loop are disclosed. The parallel amplifier has a parallel amplifier output, which is coupled to an envelope tracking power supply output via an offset capacitive element. The offset capacitive element has an offset capacitive voltage. The offset capacitance voltage control loop regulates the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis.

Claims

1. Power supply circuitry comprising:

a parallel amplifier having a parallel amplifier output coupled to an envelope tracking power supply output via an offset capacitive element, which is configured to have an offset capacitive voltage; and

an offset capacitance voltage control loop configured to regulate the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis.

2. The power supply circuitry of claim 1 further comprising a parallel amplifier power supply configured to provide a parallel amplifier power supply signal, such that the parallel amplifier is configured to regulate an envelope power supply voltage based on the parallel amplifier power supply signal.

3. The power supply circuitry of claim 1 wherein a bandwidth of the offset capacitance voltage control loop between adjacent communications slots is configured to be higher than a bandwidth of the offset capacitance voltage control loop during a communications slot.

4. The power supply circuitry of claim 1 wherein during at least one communications slot an average DC current through the offset capacitive element is equal to about zero.

5. The power supply circuitry of claim 1 further comprising switching circuitry having a switching circuitry output, wherein:

the switching circuitry output is coupled to the envelope tracking power supply output via a first inductive element;

an envelope tracking power supply has the envelope tracking power supply output and comprises the parallel amplifier, the switching circuitry, the offset capacitance voltage control loop, the first inductive element, and the offset capacitive element; and

the envelope tracking power supply is configured to provide an envelope power supply voltage to a radio frequency power amplifier via the envelope tracking power supply output, such that during envelope tracking, the envelope power supply voltage at least partially envelope tracks a radio frequency transmit signal from the radio frequency power amplifier.

6. The power supply circuitry of claim 5 further comprising a parallel amplifier power supply configured to provide a parallel amplifier power supply signal, wherein for at least one communications slot, the parallel amplifier power supply signal is based on an expected maximum and an expected minimum of the envelope power supply voltage.

7. The power supply circuitry of claim 6 wherein the offset capacitive voltage is based on the expected minimum of the envelope power supply voltage.

8. The power supply circuitry of claim 7 wherein the parallel amplifier output has a sink headroom voltage, such that the offset capacitive voltage is less than or equal to a difference between the expected minimum of the envelope power supply voltage and the sink headroom voltage.

9. The power supply circuitry of claim 8 wherein the sink headroom voltage is equal to about 0.2 volts.

10. The power supply circuitry of claim 7 wherein the parallel amplifier power supply signal has a parallel amplifier power supply voltage, such that during the at least one communications slot, the parallel amplifier power supply voltage is based on a difference between the expected maximum of the envelope power supply voltage and the expected minimum of the envelope power supply voltage.

11. The power supply circuitry of claim 10 wherein the parallel amplifier output has a source headroom voltage, such that during the at least one communications slot, the parallel amplifier power supply voltage is greater than or equal to a sum of the source headroom voltage and a difference between the expected maximum of the envelope power supply voltage and the offset capacitive voltage.

12. The power supply circuitry of claim 11 wherein the expected maximum of the envelope power supply voltage is low enough to clip the radio frequency transmit signal from the radio frequency power amplifier.

13. The power supply circuitry of claim 6 wherein the parallel amplifier power supply is further configured to receive a DC source signal from a DC power source and further provide the parallel amplifier power supply signal based on the DC source signal.

14. The power supply circuitry of claim 13 wherein the DC power source is a battery.

15. The power supply circuitry of claim 13 wherein the parallel amplifier power supply comprises a two flying capacitor-based charge pump.

16. The power supply circuitry of claim 13 wherein the parallel amplifier power supply comprises an inductor-based charge pump.

17. The power supply circuitry of claim 13 wherein:

the envelope tracking power supply is further configured to operate in one of an envelope tracking mode and an average power tracking mode;

during the envelope tracking mode, the envelope tracking power supply is further configured to provide the envelope power supply voltage to the radio frequency power amplifier via the envelope tracking power supply output, such that the envelope power supply voltage at least partially envelope tracks the radio frequency transmit signal from the radio frequency power amplifier; and

during the average power tracking mode, the envelope tracking power supply is further configured to provide the envelope power supply voltage to the radio frequency power amplifier via the envelope tracking power supply output, such that during a communications slot the envelope power supply voltage is about constant.

18. The power supply circuitry of claim 17 wherein during the envelope tracking mode:

the parallel amplifier is enabled;

the switching circuitry is enabled; and

the parallel amplifier power supply is enabled.

19. The power supply circuitry of claim 18 wherein the radio frequency power amplifier is configured to receive a power amplifier bias signal, which is based on the parallel amplifier power supply signal.

20. The power supply circuitry of claim 17 wherein during the average power tracking mode and when the envelope power supply voltage is above a voltage threshold:

the parallel amplifier is disabled;

the switching circuitry is enabled; and

the parallel amplifier power supply is enabled, such that the radio frequency power amplifier is configured to receive a power amplifier bias signal, which is based on the parallel amplifier power supply signal.

21. The power supply circuitry of claim 17 wherein during the average power tracking mode and when the envelope power supply voltage is above a voltage threshold:

the parallel amplifier is disabled;

the switching circuitry is enabled; and

the parallel amplifier power supply is disabled.

22. The power supply circuitry of claim 17 wherein during the average power tracking mode and when the envelope power supply voltage is below a voltage threshold:

the parallel amplifier is disabled;

the switching circuitry is disabled; and

the parallel amplifier power supply is enabled, such that the envelope power supply voltage is based on the parallel amplifier power supply signal.

23. The power supply circuitry of claim 22 wherein the radio frequency power amplifier is configured to receive a power amplifier bias signal, which is based on the parallel amplifier power supply signal.

24. The power supply circuitry of claim 5 wherein:

the offset capacitive element is directly coupled between the parallel amplifier output and the envelope tracking power supply output; and

the first inductive element is directly coupled between the switching circuitry output and the envelope tracking power supply output.

25. The power supply circuitry of claim 5 wherein:

the parallel amplifier further has a feedback input;

the offset capacitive element is directly coupled between the parallel amplifier output and the envelope tracking power supply output;

the first inductive element is directly coupled between the switching circuitry output and the feedback input; and

a second inductive element is directly coupled between the feedback input and the envelope tracking power supply output.

26. The power supply circuitry of claim 25 wherein the first inductive element has a first inductance and the second inductive element has a second inductance, such that a ratio of the first inductance divided by the second inductance is greater than ten.

27. The power supply circuitry of claim 5 wherein a first filter capacitive element is coupled between the envelope tracking power supply output and a ground.

28. A method comprising:

providing a parallel amplifier having a parallel amplifier output coupled to an envelope tracking power supply output via an offset capacitive element, which is configured to have an offset capacitive voltage; and

regulating the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis.