Methodology to avoid gate stress for low voltage devices in FDSOI technology

• US 9,929,728 B2
• Filed: 06/17/2016
• Issued: 03/27/2018
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Agrawal, Ankit
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US15/185,514
• Publication Number:
  US 20160301404A1
• Time in Patent Office: 648 Days
• Field of Search: None
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Claims

1. A method, comprising:

applying a first voltage to a source terminal of a first transistor in a first semiconductor layer;

applying the first voltage to a gate terminal of the first transistor, the first transistor having a respective source, a respective channel, and a respective drain;

switching the first transistor on or off by applying a switching voltage to a first portion of a second semiconductor layer that is separated from the first semiconductor layer by a dielectric layer;

applying a second voltage to a source terminal of a second transistor in the first semiconductor layer;

applying the second voltage to a gate terminal of the second transistor, the second transistor having a respective source, a respective channel, and a respective drain; and

switching the second transistor on or off by applying the switching voltage to a second portion of the second semiconductor layer.

2. The method of claim 1 wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

3. The method of claim 2 wherein the drain of the first transistor is electrically coupled to the drain of the second transistor.

4. The method of claim 3 wherein the first voltage is a high supply voltage and the second voltage is a low supply voltage.

5. The method of claim 3 wherein the first and second transistors are coupled together as an inverter having an input coupled to the first and second portions of the second semiconductor substrate and an output coupled to the respective drains of the first and second transistors.

6. The method of claim 1, further comprising applying a second voltage to the drain of the first transistor, a channel length of the first transistor being less than or equal to 32 nm, a voltage difference between the first and second voltages being at least 3 V.

7. A method, comprising:

providing a semiconductor substrate having a heavily doped region and a buried oxide layer, the buried oxide layer disposed below a first semiconductor layer and above the heavily doped region;

forming an inverter in the first semiconductor layer, the inverter including a p-type metal-oxide-semiconductor (MOS) transistor and an n-type MOS transistor;

forming first and second back gates in the heavily doped region, the first back gate underlying the p-type MOS transistor and the second back gate underlying the n-type MOS transistor;

forming first and second back gate input contacts to the first and second back gates, respectively, the first and second back gate input contacts extending through the first semiconductor layer and the buried oxide layer;

coupling a source and a gate of the p-type transistor to one another; and

coupling a source and a gate of the n-type transistor to one another.

8. The method of claim 7, further comprising

coupling the first and second back gate input contacts to one another;

forming output contacts to respective drains of each of the transistors;

coupling the output contacts to one another;

coupling the source and the gate of the p-type transistor to a power supply; and

coupling the source and the gate of the n-type transistor to an electrical ground.

9. The method of claim 7 wherein the semiconductor substrate further includes a lightly doped region, the heavily doped region being disposed on the lightly doped region.

10. The method of claim 7 wherein a thickness of the buried oxide layer exceeds 20 nm.

11. The method of claim 7 wherein a thickness of the first semiconductor layer is less than or equal to 10 nm.

15. The method of claim 7 wherein forming the first and second back gates in the heavily doped region includes forming an isolation trench extending through the first semiconductor layer, the buried oxide layer and the heavily doped region, the first and second back gates being separated by the isolation trench.

12. A method, comprising:

providing a semiconductor substrate having a heavily doped region and a buried oxide layer therein, the buried oxide layer disposed between a first semiconductor layer and the heavily doped region;

forming a p-type transistor in the first semiconductor layer, the p-type transistor having a source region, a drain region, a channel region and a gate;

forming an n-type transistor adjacent to the p-type transistor in the first semiconductor layer, the n-type transistor having a source region, a drain region, a channel region and a gate;

forming an isolation trench between the n-type and p-type transistors;

forming back gate input contacts to the heavily doped region;

forming output contacts to the drain regions of the transistors;

forming power supply contacts to the source region and the gate of the p-type transistor; and

forming ground contacts to the source region and the gate of the n-type transistor.

13. The method of claim 12, further comprising:

coupling the output contacts to one another;

coupling the power supply contacts to one another; and

coupling the ground contacts to one another.

14. The method of claim 12 wherein the source and drain regions of the transistors are doped regions have substantially vertical doping profile boundaries adjacent to the channel regions.

16. The method of claim 12 wherein a thickness of the buried oxide layer exceeds 20 nm.

17. The method of claim 12 wherein a thickness of the first semiconductor layer is less than or equal to 10 nm.

18. The method of claim 12, further comprising:

coupling the source region and the gate of the p-type transistor to one another; and

coupling the source region and the gate of the n-type transistor to one another.

19. The method of claim 12, further comprising:

forming an isolation trench through the first semiconductor layer, the buried oxide layer and the heavily doped region, the p-type transistor and the n-type transistor being separated by the isolation trench.