Efficiently managing multiple power supplies

• US 9,929,730 B2
• Filed: 03/11/2015
• Issued: 03/27/2018
• Est. Priority Date: 12/03/2014
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Spiel, Seth
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Warmflash, Michael
• Application Number:
  US14/644,742
• Publication Number:
  US 20160164516A1
• Time in Patent Office: 1,112 Days
• Field of Search: 307104, 307 80, 307 75, 307140
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/74 by the use, as active elements, of diodes by the use of more than one type of semiconductor device H03K17/567; by the use of tunnel diodes H03K17/58; by the use of negative resistance diodes H03K17/70

Abstract

An apparatus includes a first power supply switch, a second power supply switch, and a control circuit. The first power supply switch includes a P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) having a drain coupled to a first power rail to receive a first power voltage, a source coupled to an output node, and a gate to selectively turn on or off the PMOSFET to supply the first power voltage to the output node or isolate the first power rail. The second power supply switch receives a second power voltage and passes it to the output node if the second power voltage is present. The control circuit cooperates with the first power supply switch to control the gate voltage to turn on the PMOSFET if the first power voltage is present and the second power voltage is absent, and turn off the PMOSFET if the second power voltage is present.

Claims

1. An apparatus comprising:

a first power supply switch including a power P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) having a drain coupled to a first power rail to receive a first power voltage, a source coupled to an output node to power a load, and a gate to receive a gate voltage to selectively turn on or turn off the power PMOSFET to supply the first power voltage to the output node or isolate the first power rail from the output node, respectively;

a second power supply switch coupled to a second power rail to receive a second power voltage and to pass to the output node the second power voltage when present; and

a control circuit coupled to the second power rail and the gate, and that cooperates with the first power supply switch to control the gate voltage to (i) turn on the power PMOSFET if the first power voltage is present and the second power voltage is absent, and (ii) turn off the power PMOSFET if the second power voltage is present.

2. The apparatus of claim 1, wherein:

the first power supply switch is configured to drive the gate voltage to a first voltage level to turn on the power PMOSFET if the first power voltage is present and the second power voltage is absent; and

the control circuit is configured to drive the gate voltage to a second voltage level to turn off the power PMOSFET if the second power voltage is present.

3. The apparatus of claim 2, wherein:

the first voltage level creates a negative gate-source voltage of the power PMOSFET to cause the power PMOSFET to operate in a fully on saturation region; and

the second voltage level creates a gate-source voltage of the power PMOSFET to cause the power PMOSFET to operate in a fully off cut-off region.

4. The apparatus of claim 2, wherein the control circuit includes a signal PMOSFET having a source-drain (SD) path coupled between the second power rail and the gate of the power PMOSFET, and a second gate to receive a second gate voltage to turn on the SD path if the second power voltage is present, wherein the SD path, when turned on responsive to the second power voltage, passes the second power voltage to the gate of the power PMOSFET as the second voltage level to turn off the power PMOSFET.

5. The apparatus of claim 4, wherein the control circuit further includes a voltage divider having first and second series-connected resistors respectively coupled between the second power rail and the second gate and the second gate and a ground rail, wherein the voltage divider is configured to control the second gate voltage to turn on the SD path if the second power voltage is present.

6. The apparatus of claim 4, wherein a source-drain path of the power PMOSFET is wider than the source-drain path of the signal PMOSFET when the power and signal PMOSFETS respectfully operate in fully-on saturated regions.

7. The apparatus of claim 2, wherein the first power supply switch includes a voltage divider having first and second series-connected resistors respectively coupled between the first power rail and the gate and the gate and a ground rail, wherein the voltage divider is configured to drive the gate voltage to the first voltage level to turn on the power PMOSFET if the first power voltage is present and the second power voltage is absent.

8. The apparatus of claim 7, wherein the control circuit includes a signal PMOSFET having a source-drain (SD) path coupled between the second power rail and the power PMOSFET gate, and a second gate to receive a second gate voltage to turn on the SD path if the second power voltage is present, wherein the SD path, when turned on responsive to the second power voltage, provides the second power voltage to the gate as the second voltage level to turn off the power PMOSFET.

9. The apparatus of claim 1, wherein the power PMOSFET includes an internal body diode configured to forward conduct in a direction from the drain to the source of the power PMOSFET.

10. An apparatus comprising:

a first power supply switch including a power P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) having a first drain coupled to a first power rail to receive a first power voltage, a first source coupled to an output node to power a load, and a first gate;

a second power supply switch coupled to the output node and a second power rail to receive a second power voltage, the second power supply switch to provide to the output node the second power voltage when present; and

a control circuit including;

a signal PMOSFET having a source-drain (SD) path coupled between the second power rail and the first gate, and a second gate; and

a first voltage divider having first and second series-connected resistors respectively coupled between the second power rail and the second gate and the second gate and a ground rail.

11. The apparatus of claim 10, wherein the first power supply switch further includes:

a second voltage divider having third and fourth series-connected resistors respectively coupled between the first power rail and the first gate and the first gate and the ground rail.

12. The apparatus of claim 11, wherein:

the second voltage divider is configured to drive a gate voltage at the first gate to a first voltage level to turn on the power PMOSFET if the first power voltage is present and the second power voltage is absent; and

the signal PMOSFET is configured to drive the gate voltage to a second voltage level to turn off the power PMOSFET if the second power voltage is present.

13. The apparatus of claim 12, wherein a source-drain path of the power PMOSFET is wider than the source-drain path of the signal PMOSFET when the power and signal PMOSFETS respectfully operate in fully-on saturated regions.

14. The apparatus of claim 12, wherein:

the first voltage level creates a negative gate-source voltage of the power PMOSFET to cause the power PMOSFET to operate in a fully on saturation region; and

the second voltage level creates a gate-source voltage of the power PMOSFET to cause the power PMOSFET to operate in a fully off cut-off region.

15. The apparatus of claim 12, wherein the first voltage divider is configured to control a second gate voltage applied to the second gate of the signal PMOSFET to turn on the SD path of the signal PMOSFET if the second power voltage is present, wherein the SD path, when turned on responsive to the second power voltage, passes the second power voltage to the gate of the power PMOSFET as the second voltage level to turn off the power PMOSFET.

16. The apparatus of claim 10, wherein the power PMOSFET includes an internal body diode configured to forward conduct in a direction from the drain to the source of the power PMOSFET.

17. The apparatus of claim 10, wherein:

the first power supply switch is configured to drive a first gate voltage of the first gate to a first voltage level to turn on the power PMOSFET if the first power voltage is present and the second power voltage is absent; and

the control circuit is configured to drive the first gate voltage of the first gate to a second voltage level to turn off the power PMOSFET if the second power voltage is present.