Low power, centralized data collection

• US 9,929,771 B2
• Filed: 02/02/2017
• Issued: 03/27/2018
• Est. Priority Date: 02/05/2016
• Status: Active Grant

• Current Assignee: Hydropoint, HydroPoint Data Systems Inc., Hyropoint Data Systems Incorporated
• Original Assignee: APANA, Inc.
• Inventors: Rose, Matthew W., Burns, Frank, Peterson, Matthew Maher, Peckham, Canyon Daniel, Siderskiy, Valentin, Humphrey, David Royce, Remmers, Thomas
• Primary Examiner(s): JACKSON, BLANE J
• Application Number:
  US15/423,500
• Publication Number:
  US 20170230074A1
• Time in Patent Office: 418 Days
• CPC Class Codes: G01D 4/004 Remote reading of utility meters to a fixed location
• CPC Class Codes: H02J 7/0014 Circuits for equalisation of charge between batteries
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/1036 with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters H04B1/123 takes precedence; filter circuits H03H
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 2001/0408 with power amplifiers
• CPC Class Codes: H04W 52/0277 according to available power supply, e.g. switching off when a low battery condition is detected
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks
• CPC Class Codes: H04W 88/02 Terminal devices
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: H04W 88/16 Gateway arrangements
• CPC Class Codes: Y02B 90/20 Smart grids as enabling technology in buildings sector smart grids supporting the management or operation of end-user stationary applications in general, or like technologies with no associated climate change mitigation effect Y04S20/00
• CPC Class Codes: Y04S 20/30 Smart metering, e.g. specially adapted for remote reading

Abstract

The systems and methods described herein are directed to techniques for improving battery life performance of end devices in resource monitoring systems which transmit data using low-power, wide area network (LPWAN) technologies. Further, the techniques include providing sensor interfaces in the end devices configured to communicate with multiple types of metrology sensors. Additionally, the systems and methods include techniques for reducing the size of a concentrator of a gateway device which receives resource measurement data from end devices. The reduced size of the concentrator results in smaller, more compact gateway devices that consume less energy and reduce heat dissipation experienced in gateway devices. The concentrator may comply with modular interface standards, and include two radios configured for transmitting 1-watt signals. Lastly, the systems and methods include techniques for fully redundant radio architecture within a gateway device, allowing for maximum range and minimizing downtime due to transmission overlap.

Claims

1. A concentrator chip comprising:

a printed circuit board (PCB);

a first antenna connector and a second antenna connector;

at least one processor, disposed on the PCB, and configured to perform power functions and interfacing functions for the concentrator chip;

a baseband processor, disposed on the PCB, and configured to control a first radio of the concentrator chip and a second radio of the concentrator chip;

the first radio, disposed on the PCB, comprising;

a first front-end transceiver to process a first signal at a first frequency; and

a first transmit path including a first power amplifier to amplify, as a first amplified signal, the first signal received from the first front-end transceiver and pass the first amplified signal to the first antenna connector for transmission;

the second radio, disposed on the PCB, comprising;

a second front-end transceiver to process a second signal at a second frequency; and

a second transmit path including a second power amplifier to amplify, as a second amplified signal, the second signal received from the second front-end transceiver and pass the second amplified signal to the second antenna connector for transmission; and

a power supply, disposed on the PCB, controlled by the at least one processor and configured to provide power to the first power amplifier and the second power amplifier,

wherein the concentrator chip is configured to be removably coupled to a computing device and to transmit and receive signals to one or more sensors for collecting resource consumption data, the concentrator chip further configured for providing the resource consumption data to one or more centralized server computers.

2. The concentrator chip of claim 1, further comprising computer-readable media storing computer-executable instructions that, when executed by the at least one processor, cause the at least one processor to perform acts comprising:

causing the power supply to provide power at a first voltage of approximately 5 volts to the first power amplifier, wherein the first voltage causes the first power amplifier to saturate at a saturation voltage associated with the first power amplifier, to output a first output radio frequency (RF) signal at a first signal power of approximately 1-watt; and

causing the power supply to provide power at a second voltage of approximately 5 volts to the second power amplifier, wherein the second voltage causes the second power amplifier to saturate at a saturation voltage associated with the second power amplifier, to output a second output RF signal at a second signal power of approximately 1-watt.

3. The concentrator chip of claim 2, the acts further comprising:

transmitting the first output RF signal over a first period of time; and

transmitting the second output RF signal over a second period of time, wherein the first period of time and the second period of time at least partially overlap.

4. The concentrator chip of claim 1, further comprising computer-readable media storing computer-executable instructions that, when executed by the at least one processor, cause the at least one processor to perform acts comprising:

causing the power supply to provide power at a third voltage of approximately 3.75 volts to the first power amplifier, wherein the third voltage causes the first power amplifier to saturate at a saturation voltage associated with the first power amplifier, to output a first radio frequency (RF) RF signal at a first signal power of approximately ½

-watt; and

causing the power supply to provide power at a fourth voltage of approximately 3.75 volts to the second power amplifier, wherein the fourth voltage causes the second power amplifier to saturate at a saturation voltage associated with the second power amplifier, to output a second RF signal at a second signal power of approximately ½

-watt.

5. The concentrator chip of claim 1, wherein:

the first frequency is approximately 902 megahertz; and

the second frequency is approximately 928 megahertz.

6. The concentrator chip of claim 1, wherein a volume of the concentrator chip is less than 0.25 in³.

7. The concentrator chip of claim 1, wherein the first radio and the second radio are configured to communicate using a low-power, wide area network (LPWAN) protocol.

8. A concentrator chip comprising:

a printed circuit board (PCB);

at least one processor, disposed on the PCB, and configured to perform power functions and interfacing functions for the concentrator chip;

a multi-pin header module electrically coupled to at least one processor and removably coupled to a gateway device;

multiple switching power supplies electrically coupled to the at least one processor;

a baseband processor, disposed on the PCB, and configured to control a first radio of the concentrator chip and a second radio of the concentrator chip;

the first radio, disposed on the PCB, comprising;

a first transceiver;

a first transmission path for transmitting one or more first signals; and

a first receive path for receiving one or more second signals;

the second radio, disposed on the PCB, comprising;

a second transceiver;

a second transmission path for transmitting one or more third signals; and

a second receive path for receiving one or more fourth signals;

a first antenna connector to transmit the one or more first signals for the first radio and to receive the one or more second signals for the first radio; and

a second antenna connector to transmit the one or more third signals for the second radio and to receive the one or more fourth signals for the second radio;

wherein a volume of the concentrator chip is less than 0.25 inches cubed.

9. The concentrator chip of claim 8, wherein dimensions of the PCB including components disposed thereon comprise:

a height of approximately 0.19 inches;

a length of approximately 1.30 inches; and

a width of approximately 0.96 inches.

10. The concentrator chip of claim 8, wherein;

the first transmission path comprises a first balun, a first power amplifier, and a first low-pass filter; and

the second transmission path comprises a second balun, a second power amplifier, and a second low pass-filter.

11. The concentrator chip of claim 10, wherein:

the first receive path includes a first surface acoustic wave (SAW) filter, a first low-noise amplifier (LNA), and a second SAW filter; and

the second receive path includes a third SAW filter, a second LNA, and a fourth SAW filter.

12. The concentrator chip of claim 8, wherein:

the first radio further comprises;

a first switch, controllable by the baseband processor, to select between the first transmission path and the first receive path; and

a first lumped element low-pass filter disposed between the first switch and the first antenna connector; and

the second radio further comprises;

a second switch, controllable by the baseband processor, to select between the second transmission path and the second receive path; and

a second lumped element low-pass filter disposed between the second switch and the second antenna connector.

13. The concentrator chip of claim 8, further comprising:

a first oscillator configured to control a clock rate of the at least one processor; and

a second oscillator configured to control a clock rate of the baseband processor, wherein a first frequency of the first oscillator is lower than a second frequency of the second oscillator.

14. The concentrator chip of claim 8, further comprising a flash memory.

15. A concentrator chip comprising:

a printed circuit board (PCB);

at least one processor, disposed on the PCB, and configured to perform power functions and interfacing functions for the concentrator chip;

a baseband processor, disposed on the PCB, and configured to control a first radio of the concentrator chip and a second radio of the concentrator chip;

the first radio, disposed on the PCB, comprising;

a first transceiver;

a first transmission path for transmitting one or more first signals, the first transmission path including a first power amplifier; and

a first receive path for receiving one or more second signals;

the second radio, disposed on the PCB, comprising;

a second transceiver;

a second transmission path for transmitting one or more third signals, the second transmission path including a second power amplifier; and

a second receive path for receiving one or more fourth signals;

a first antenna connector to transmit the one or more first signals for the first radio and to receive the one or more second signals for the first radio;

a second antenna connector to transmit the one or more third signals for the second radio and to receive the one or more fourth signals for the second radio; and

computer-readable media storing computer-executable instructions that, when executed by the baseband processor, causes the baseband processor to perform acts comprising;

generating a first signal as the one or more first signals for transmission by the first radio via the first antenna connector;

inputting the first signal into the first radio to cause the first signal to be transmitted via the first antenna connector, the first signal being transmitted for a first period of time;

generating a second signal as the one or more third signals for transmission by the second radio via the second antenna connector; and

inputting the second signal into the second radio to cause the second signal to be transmitted via the second antenna connector, the second signal to be transmitted for a second period of time,

wherein the first period of time and the second period of time at least partially overlap.

16. The concentrator chip of claim 15, further comprising:

a switching supply to provide power to the first power amplifier and the second power amplifier; and

wherein the computer-executable instructions, when executed by the at least one processor, further cause the at least one processor to perform operations comprising;

causing the switching supply to provide power at a first voltage of approximately 5 volts to the first power amplifier, wherein the first voltage causes the first power amplifier to saturate at a first power amplifier saturation voltage to output a first radio frequency (RF) output signal at a power of approximately 1-watt; and

causing the switching supply to provide power at a second voltage of approximately 5 volts to the second power amplifier, wherein the second voltage causes the second power amplifier to saturate at a second power amplifier saturation voltage to output a second RF output signal at a power of approximately 1-watt.

17. The concentrator chip of claim 15, further comprising:

a switching supply to provide power to the first power amplifier and the second power amplifier;

wherein the computer-executable instructions, when executed by the at least one processor, further cause the at least one processor to perform operations comprising;

causing the switching supply to provide power at a first voltage to the first power amplifier, wherein the first voltage causes the first power amplifier to amplify the first signal to a first power; and

causing the switching supply to provide power at a second voltage to the second power amplifier, wherein the second voltage causes the second power amplifier to amplify the second signal to a second power,

wherein the first voltage is different than the second voltage, and the first power is different than the second power.

18. The concentrator chip of claim 15, wherein:

the first signal is transmitted at a first frequency of approximately 902 megahertz; and

the second signal is transmitted at a second frequency of approximately 928 megahertz.

19. The concentrator chip of claim 15, wherein a volume of the concentrator chip is less than 0.25 inches cubed.

20. The concentrator chip of claim 15, wherein the first radio and the second radio are configured to communicate using a low-power, wide area network (LPWAN) protocol.