Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication

• US 9,929,818 B2
• Filed: 07/07/2015
• Issued: 03/27/2018
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Bus, SA
• Inventors: Holden, Brian, Shokrollahi, Amin
• Primary Examiner(s): Bolourchi, Nader
• Application Number:
  US14/793,448
• Publication Number:
  US 20150381346A1
• Time in Patent Office: 994 Days
• Field of Search: 375257
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: H04B 17/364 Delay profiles
• CPC Class Codes: H04B 3/00 Line transmission systems combined with near-field transmission systems H04B5/00
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04B 5/26 using coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0643 block codes
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 7/043 Pseudo-noise [PN] codes variable during transmission synchronisation of spread spectrum receivers H04B1/69
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Methods and systems are described for communication of data over a communications bus at high speed and high pin efficiency, with good resilience to common mode and other noise. Pin efficiencies of 100% may be achieved even for bus widths of four or fewer wires. Information to be transmitted is encoded as words of a vector signaling code, each word comprising multiple values transmitted as a group over the communications bus. Subsets of the vector signaling code have distinct group characteristics, which are discernable on transmission and are used to facilitate decoding on reception.

Claims

1. An apparatus comprising:

an encoder configured to map a set of information bits into a code word of a respective subcode among a plurality of subcodes that collectively comprise a vector signaling code, each subcode among the plurality of subcodes comprising multiple code words, the plurality of subcodes including a first unbalanced subcode and a second unbalanced subcode, wherein a sum of analog voltages representing the first unbalanced subcode is opposite in sign to a sum of analog voltages representing the second unbalanced subcode; and

an output driver operative to transform the code word into physical signals on multiple transmission elements of a data bus.

2. The apparatus of claim 1, wherein a collection of all code words across all subcodes in the plurality of subcodes is balanced.

3. The apparatus of claim 1, further comprising at least one compensation transmitter configured to transmit a physical signal derived from a transmission element into a dummy load for purposes of compensating for simultaneous switching noise.

4. The apparatus of claim 3, wherein the compensation transmitter is located in a pad ring of an integrated circuit.

5. The apparatus of claim 3, wherein the at least one compensation transmitter comprises a compensation circuit that observes a load that is placed on a plurality of driven circuits and adjusts parameters of the dummy load to more closely match the load that is placed on the driven circuits.

6. The apparatus of claim 1, wherein a number of code words in the vector signaling code is greater than a number of possible combinations of the set of information bits, the code words in excess of the number of possible combinations being excess code words.

7. The apparatus of claim 6, wherein mapping values of the code word includes using at least one excess code word to reduce a length of runs of a same value of a transmission element.

8. The apparatus of claim 6, wherein the encoder is configured to use at least one excess code word to improve a long-term balance of a transmission element.

9. The apparatus of claim 6, wherein the encoder is configured to use at least one excess code word to provide an error check function over the set of information bits.

10. The apparatus of claim 6, wherein the encoder is configured to use at least one excess code word to provide an additional communications channel.

11. The apparatus of claim 6, wherein the encoder is configured to use at least one excess code word to provide link-specific control signaling.

12. An apparatus comprising:

a plurality of sample circuits operative to receive an input by sampling physical signals on the transmission elements;

a first decoder configured to identify, based on the received input, a subcode from among a plurality of subcodes that collectively comprise a vector signaling code, each subcode among the plurality of subcodes comprising multiple code words, the plurality of subcodes including a first unbalanced subcode and a second unbalanced subcode, wherein a sum of analog voltages representing the first unbalanced subcode is opposite in sign to a sum of analog voltages representing the second unbalanced subcode; and

a second decoder configured to (i) identify, based on the received input, a code word within the identified subcode and to (ii) provide an output result based on the identified code word.

13. The apparatus of claim 12, wherein the first decoder is configured to evaluate an analog sum of the physical signals and to identify the subcode based on the analog sum.

14. The apparatus of claim 12, wherein the first decoder is configured to evaluate a sum of absolute values of differences between the physical signals and to identify the subcode based on the sum.

15. The apparatus of claim 12, wherein the first decoder is configured to identify the physical signals with the lowest signal difference and to identify the subcode based on the identification of the physical signals with the lowest signal difference.

16. The apparatus of claim 12, wherein the first decoder is configured to produce a subcode discriminator result, and the second decoder is operative to provide a maximum likelihood assessment of the values of the received input and the subcode discriminator result.

17. The apparatus of claim 13, wherein identifying the subcode comprises comparing the analog sum of the physical signals with a fixed reference.

18. The apparatus of claim 13, wherein identifying the subcode comprises comparing the analog sum of the physical signals with a time-average of the analog sum.

19. The apparatus of claim 13, wherein identifying the subcode comprises comparing the analog sum of the physical signals with a stored value of at least one known input signal at a previous time.

20. The apparatus of claim 13, wherein identifying the subcode comprises comparing an average of the physical signals with a stored value of at least one known input signal at a previous time.