Power up of semiconductor device having a temperature circuit and method therefor

• US 9,933,317 B2
• Filed: 11/11/2015
• Issued: 04/03/2018
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/938,433
• Publication Number:
  US 20160064064A1
• Time in Patent Office: 874 Days
• Field of Search: 36518911, 36518905, 365227
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Claims

1. A method of operating a semiconductor device having a temperature circuit that provides a temperature window comprising the steps of:

initializing the temperature circuit to provide a first temperature window from a plurality of temperature windows in response to transitioning a power supply from a first potential to a second potential;

by operation of detecting circuits on the semiconductor device, detecting if a temperature of the semiconductor device is outside of the first temperature window; and

if the semiconductor device temperature is outside of the first temperature window, adjusting the temperature circuit to provide a second temperature window from the plurality of temperature windows that includes the device temperature;

wherein

the first temperature window has an adjacent lower temperature window and an adjacent higher temperature window in the plurality of temperature windows.

2. The method of operating the semiconductor device of claim 1, wherein:

the semiconductor device is a semiconductor memory device.

3. The method of operating the semiconductor device of claim 1, wherein:

at least one of the first, second or other temperature window is provided in accordance with a value and the value includes at least 4 binary bits.

4. The method of operating the semiconductor device of claim 3, wherein:

the value includes at least 5 binary bits.

5. The method of operating the semiconductor device of claim 3, wherein:

at least a portion of the first temperature window and a portion of at least one of the adjacent temperature windows overlaps.

6. The method of operating the semiconductor device of claim 1, wherein:

the step of adjusting includes incrementally changing a count value provided by a counter circuit.

7. The method of operating the semiconductor device of claim 6, further including the step of:

providing performance parameters from a performance parameter table based on the count value provided by the counter circuit after the step of adjusting the temperature circuit.

8. The method of operating the semiconductor device of claim 7, further including the step of:

generating a read signal after the step of adjusting the temperature circuit and the performance parameter table provides the performance parameters in response to the read signal.

9. The method of operation the semiconductor device of claim 1, wherein:

the first temperature window and the second temperature window are separated by at least one other temperature window from the plurality of temperature windows.

10. A method of operating the semiconductor device having a temperature circuit that provides a temperature window comprising the steps of:

initializing the temperature circuit to provide a first temperature window from a plurality of temperature windows in response to transitioning a power supply from a first potential to a second potential;

by operation of detecting circuits on the semiconductor device, detecting if a temperature of the semiconductor device is outside of the first temperature window; and

if the semiconductor device temperature is outside of the first temperature window, adjusting the temperature circuit to provide a second temperature window from the plurality of temperature windows that includes the device temperature;

wherein

the first temperature window is at about a midpoint of a plurality of potential temperature windows in which the semiconductor memory device can operate, and

the semiconductor device is a memory device.

11. A method of operating a semiconductor device having a temperature circuit that provides a temperature window comprising the steps of:

initializing the temperature circuit to provide a first temperature window from a plurality of temperature windows in response to transitioning a power supply from a first potential to a second potential, wherein the device has a device temperature that is outside the first temperature window;

by operation of detecting circuits on the semiconductor device, detecting if a temperature of the semiconductor device is outside of the first temperature window; and

adjusting the temperature circuit to provide a second temperature window from the plurality of temperature windows that includes the device temperature, wherein the first temperature window and the second temperature window are separated by at least one other temperature window from the plurality of temperature windows;

wherein

the first temperature window has an adjacent lower temperature window and an adjacent higher temperature window in the plurality of temperature windows.

12. The method of operating the semiconductor device of claim 11, wherein:

the semiconductor device is a semiconductor memory device.

13. The method of operating the semiconductor device of claim 12, wherein:

the semiconductor memory device is a dynamic random access memory device.

14. The method of operating the semiconductor device of claim 13, wherein:

the first temperature window is at about a midpoint of a plurality of potential temperature windows in which the semiconductor memory device can operate.

15. The method of operating the semiconductor device of claim 11, wherein:

at least one of the first temperature window, second temperature window, or another of the plurality of temperature windows is provided in accordance with a value and the value includes at least 4 binary bits.

16. The method of operating the semiconductor device of claim 15, wherein:

the value includes at least 5 binary bits.

17. The method of operating the semiconductor device of claim 15, wherein:

at least a portion of the first temperature window and a portion of at least one of the adjacent temperature windows overlaps.

18. The method of operating the semiconductor device of claim 15, wherein:

the value is provided by a counter circuit and the step of adjusting includes incrementally changing the value.

19. The method of operating the semiconductor device of claim 18, wherein:

providing performance parameters from a performance parameter table based on the value provided by the counter circuit after the step of adjusting the temperature circuit.

20. The method of operating the semiconductor device of claim 11, wherein:

the semiconductor device is a processor.